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Everything posted by artvvb

  1. Inclusion of the ps7_init and HDF file in the application project src folder (and the ps7_cortexa9_0 folder in the _today project) looks very strange to me. It also seems to have caused a lot of errors when I opened the workspace and built it on my system, so I am not sure if something strange happened when sharing the workspace. If this reflects what you have on your system, you could try just creating a new Hello World application project to confirm that the exported hardware is valid, and that you can program and communicate with your board. <-- This is what I would expec
  2. Needed to double check. Have you connected a serial terminal (Tera Term or whatever)? If so, what is being printed by the demo? For what it's worth, I've seen similar projects halt on "printf" statements before, depending on Vivado version and the board used. xil_printf generally works fine, but does not accept floats. Here's a diff of a fix for that issue. Could you zip and share your SDK workspace?
  3. Have you programmed the hardware and run the demo application in Xilinx SDK? Both the hardware and software must be running on the board to get an image.
  4. Looks like the board may be booting the out-of-box demo from QSPI flash. It is still possible to program it while this is happening, but you may still want to move the JP6 jumper to JTAG mode. -Arthur
  5. I believe that there is a bug in that particular version of the dvi2rgb decoder. A workaround would be to just set the TMDS clock range parameter to ">= 120 MHz". Alternatively, you could replace the core in the project's repo folder with the latest version of that IP, which has resolved that bug, found in this ZIP. Thanks, Arthur
  6. This error is likely related to the rgb2dvi IP. Please send a screenshot of its configuration (see below).
  7. Looks like the project was just missing constraints. I am unsure what the root cause of the problem is, but I managed to generate a bitstream. Download the attached XDC file and add it to your project. Thanks, Arthur Zybo-Z7-Master.xdc
  8. Hi @Dareamol Open the Zynq Processing Blocks's configuration wizard. Within this, there is a tab called "MIO Configuration". Expand the "I/O Peripherals" section and scroll down to "SPI 0" and "SPI 1". The checkboxes on these lines can be used to enable the modules. The "IO" dropdown can be used to select what pins the modules control. In the case of the Zybo Z7-10, these modules must be connected to EMIO, which connects the SPI interfaces to the Zynq's programmable logic. From there, you can make these interfaces external and connect them to whatever external pins through your constraint
  9. Please use File -> Archive Project in Vivado to create a ZIP of the project. It should pick up dependencies outside of the project folder, in addition to the project folder itself. Unfortunately, projects (particularly those using create_project style scripts) are not easily portable between different versions of Vivado. As stated in the HDMI demo's wiki page, Vivado 2016.4 must be used to run the create_project script. The demo's release for 2018.2, found via the GitHub readme here, should at least be openable in any version of Vivado 2018.2 or newer, though problems may occur wh
  10. Hi @johnsan1 As there is only one UART link between the PC and your board, you cannot use more than one instance of Tera Term. I am assuming you have a Vivado block design containing two Pmod AD2 IP cores. The provided SDK example code only configures and reads from one AD2. In order to view samples from both AD2's at the same time, you must edit the example code to configure and control both AD2s and print data from both out over the serial interface. A starting point would be to add a second device driver instance to the code by editing line 44 of the example code as follows:
  11. Hi @tekson I believe that this issue may be related to capitalization of the port names in the constraint file. This is easily correctable by comparing the [get_ports <name>] names in the XDC file to the port map in the block design's *_wrapper.v file, and editing the names in the XDC to match the wrapper. Both files can be found in the Sources / Hierarchy pane in Vivado. If you provide a link to the materials you are working from on our wiki or github, I should be able to correct the issue. Thanks, Arthur
  12. When using a Pmod IP core, only I2C Pmods have their pullups enabled, all others use neither by default. The resistors can be enabled by adding a constraint file to the project and entering a line something like the following: set_property PULLUP TRUE [get_ports ja_pin1_io] set_property PULLDOWN TRUE [get_ports ja_pin2_io] Using this method for the I2C Pmods might cause some issues, depending on how Vivado handles the constraint file order. Thanks, Arthur
  13. Hi @Dareamol It depends on the constraints used in your design. Internal pullups and pulldowns can be enabled by modifying the implemented design, or by modifying the constraint file/s. By default the pins have both pullups and pulldowns disabled. Thanks, Arthur
  14. Hi @aadgl DMA is fast enough. At least when there is little else using the DDR, Xilinx's AXI DMA IP can handle data rates significantly higher than your requirement (See the Performance section of its datasheet). I've only built projects with the AXI DMA from scratch on Zynq devices before, which do not use the MIG, so I'm not certain how to go about connecting the MIG to the DMA. I believe that there is at least one demo for the Nexys Video that could be used as reference. Getting it all set up for the first time can be tricky. If you have questions, we're happy to help.
  15. Welcome to the forum, @vahid There is a lot of good information in this thread on the Xilinx forums. I've attached a Vivado 2019.1 project with a very simple VHDL testbench. Thanks, Arthur
  16. Microblaze (or some other soft processor) is almost totally necessary to configure many of Xilinx's IPs. While it's possible to create an AXI master, the interface is complex, and the IP drivers provided in SDK are a big help. Thanks, Arthur
  17. Hi @johnsan1 Microblaze does not support sleep.h in some older versions of Vivado. A nearly equivalent set of functions can be found in microblaze_sleep.h, though it may not include microsecond sleeps. Thanks, Arthur
  18. Hi @Abhijit Your block design appears to be on the right track, but the AXI VDMA requires extensive configuration via it's S_AXI_LITE interface. Controlling the AXI interface requires a microblaze processor to accomplish. If you haven't used Microblaze before, the Getting Started With IPI guide would probably be a good place to start. We have a few example designs for video applications using a similar approach to what you have started, but these typically target HDMI ports and use Zynq-based boards (example). It should be possible to get one of these designs fit what you need by rep
  19. Hi @HasanWAVE Pin 14 won't work with the Arty Z7, as it corresponds to MIO 14, which is connected to the UART on the Arty Z7, rather than a button or switch. The Arty Z7 doesn't have any switches/buttons/LEDs connected to the Zynq's MIO pins. This means that to use the PS GPIO, you need to enable GPIO EMIO (extended MIO), which routes its signals through the PL. This allows you to connect and constrain the EMIO GPIO pins as you would any other GPIO interface in the IP Integrator. Unfortunately the EMIO can't be connected to the components in the board files, however, you can s
  20. artvvb

    Custom IP

    Howdy, You can absolutely connect a custom module to an AXI GPIO, though, as [email protected] mentioned, it is not the optimal choice. To connect the outputs of a custom module to the board's LEDs: Select your module's LED pin, right click on it, and click "Make External". Note the name of the new port that gets created, then uncomment and edit the line/s of the master XDC file that correspond to the LED to use the port's name. If you expand the AXI GPIO IP's GPIO interface, you can see the individual ports that make it up (*_i, *_o, *_t). These ports can be connected to a custom module manu
  21. To add a little bit to what Jon said, these warnings appear to be ignorable. They all relate to design choices made when connecting custom IP in the block design. Typically, even when designing with Xilinx IP, many warnings are seen in the project. These messages are there to help get information on why something may be causing bigger problems later (errors, critical warnings, something not working in actual hardware). Note that even some critical warnings may be ignored. -Arthur
  22. Hi @Rickdegier, Welcome to the Digilent forums! I am not the most confident on this topic, but I have used the DMA some. The most important facet here is to make sure that your buffer is actually contained in the DDR memory. Different parts of the program can be placed in different memories using the linker script in your application project's src folder (lscript.ld). You should check that file to make sure that your global arrays are placed in the DDR. Second, if the data cache is enabled (likely), you should make sure to flush and invalidate the buffer memory area around your Simpl
  23. It looks like you have vivado-library included correctly. For vivado-boards, please go to Settings -> Project Settings -> General -> Project Device. "Zedboard" should show up in this field. Click the "...", when the "Select Device" wizard shows up, it should have the Zedboard selected. Could you confirm that the "vendor" column shows "", not "". If it shows avnet, select the digilent version instead, if the digilent version doesn't show up at all, please refer to the link in my previous comment. I suspect that you installed the digilent board files, but
  24. Hi @jackn, Apologies for the slow response. I have a few questions: What version of Vivado are you using? Are you using Avnet's board files for the Zedboard? In order to use the Pmod CAN IP core, you will need to use our board files. Installation instructions can be found on our wiki, at this link. How did you add the Pmod CAN IP core to your project? Did you follow this tutorial? If so, which release did you download? It is somewhat strange that Vivado can find the Pmod CAN IP core, but cannot find the Pmod interface (located in the if/ subdirectory of the release). These
  25. @BYTEMAN My only major concern with the your current flow is that it is still relatively difficult to gain access to any control signals you might want to use. The Language Template GUI (which you can find in the Project Manager section of the Flow Navigator) has some boilerplate code for an AXI port map with customized parameters that you can add to your custom module. THis doesn't come with the actual AXI control template, but combining the syntax for the portmap with the IP you've created, you should be able to create the same design with only a single added module. AFAIK, added module