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About artvvb

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  1. Welcome to the forums! `[email protected](negedge sclk0 & send == 1)` is likely to be causing problems. First, you are already preventing the process's logic from happening by wrapping the contents of the process in an `if (send == 1)`, making the `send==1` redundant. Additionally, I'm not positive what the `&` ends up actually representing. Avoid mixing clocks and other signals in sensitivity lists. Second, sclk0 is generated in logic, and cannot be routed on the dedicated clock lines of the FPGA. I'd recommend using the `posedge clock` here, with an additional flag to enable the
  2. Hi Dave, The board files lock in the some of the IP settings. The number of slaves can't be changed when using the board files to constrain the SPI bus, since the board.xml interface and the part0_pins.xml constraints only specify a single chip select pin. I'd recommend using Make External on the relevant pins of the AXI Quad SPI's SPI port, and constraining them all yourself. For what its worth, it looks like clearing the interface selection to Custom in the IP's Board tab will preserve all of the other settings. It may also be necessary to manually add IO buffers into the design (
  3. Hi @davec I don't see anything wrong with your hardware design or the board files. So I spun up a similar design with port J6, working from the polled_example (Vivado/Vitis 2020.1 and version 4.6 of the xspi drivers). Debugging the modifications showed a problem where XSpi_Transfer was silently failing when checking if a slave was selected in the driver, and finding none. Make sure you are calling XSpi_SetSlaveSelect. See my main.c, below. #include "xspi.h" #include "xparameters.h" #include "xil_printf.h" #include "sleep.h" int main() { xil_printf("Hello World!\r\n"); XSpi device;
  4. I am nearly certain that the DRCs are caused by the incorrect settings. It's likely that opening the configuration wizard and following until the end with default settings to regenerate the core would create issues. A MIG for which the configuration wizard has not been stepped through appears to keep its settings from the board file. Looks like you have the correct file. According to appropriate documentation, linked below, you are correct. That said, I am fairly certain that have seen the MIG work when using the default BUFG global clock buffer selection. Recommended MIG set
  5. Hi @Erick In order for the processor to be able to read data from a module, the module needs to have a memory mapped interface connected to the processor, so that the processor can read or write register data through the addresses that have been assigned to the module's interface. For microblaze, this would (usually) be an AXI interface. This guide should be able to get you started, but is fairly out-of-date, and only handles data written from a processor to an IP. Fair warning, this is a pretty broad topic, and you can find plenty of posts on this forum, and elsewhere on the web, about d
  6. Hi @okonomiyonda Some MIG configuration wizard settings terminology: The "Clock Period" setting is the period of the actual clock for the DDR interface. "Input Clock Period" is the period of the clock connected to sys_clk_i. There may be some issues with importing the board file MIG project in 2020.1, the MIG project file specifies 166.667 for Arty A7, while the configuration wizard shows a default of 333.333 (Plus, when selecting the MIG clock pins in IPI, 100MHz frequencies are shown). I can confirm that implementation can be completed with a MIG with default settings, changing
  7. Hi Tim, Some more info, I've been working on getting the Pmod IPs updated to 2020.1. A working branch is available on GitHub here: So far, I've updated most of the Makefiles on this branch, but have not yet updated the software drivers. Thanks, Arthur
  8. @bobsmith The Arty Z7's Reference Manual (Basic I/O and Shield Connector sections) and Schematic (sheets 1, 2, and 9) have information on how these components are connected. All four buttons are connected to pins on FPGA Bank 35 with resistors to pull down the pin while the button is open, and protect the FPGA pin from the voltage rail while the button is closed. IO pins 0-13 are connected to FPGA Bank 34 via current limiting resistors. The buttons can be noisy, so it may be worthwhile to debounce their signals, if you are not doing so already. Checking the debouncer output on a
  9. artvvb

    Eclypse Z7 Repository

    @mgberry Thanks for pointing this out. This also affects several nested dependencies of the hw directory (vivado-library and digilent-vivado-scripts). Using git submodule update --init --recursive in the root Eclypse-Z7 directory (instead of submodule init then submodule update) will pick up all of the nested dependencies. I'm looking into getting the appropriate documentation revised. -Arthur
  10. Hi @edge30 Using Vivado/SDK 2019.1, I tested out the Xilinx interrupt mode example for xuartps using a Zybo Z7-20 (I'm working from home, and don't have all of the hardware I would normally have access to). The Zynq PS on this board is functionally the same as the one on the Cora Z7-10. Note that this is the same example project used by the original poster in this thread, and is available through the system.mss file in a compatible project. My block design contains only the Zynq PS with the default configuration from the board files, with AXI GP0 and FCLK 0 disabled. The PL is not used wh
  11. @Paul Chang I can confirm that you are using the correct flow to get the project. There aren't any licensing concerns around either the smartconnect or fifo generator IPs. I may be able to get some more information from the errors in the third image (Windows 10), if you expand the [IP Flow 19-167] error, or if you upload a log file for that project. However, since each of the errors that show up in your screenshots appear to be related to files inside of the Xilinx installation directory, I'd recommend that you reach out to them on their Forums. Apologies, Arthur
  12. artvvb

    UART interface in Zedboard

    Hi @Anji The Zedboard's UART interface is part of the Zynq PS (Processing System). If you are using our board files, then it is enabled by default in the Zynq preset that gets applied through Block Automation. This means that the current design should already be able to receive UART data into the PS. You can use the xuartps drivers in Xilinx SDK in order to receive data. Tera Term has a menu option for transferring files (File -> Send File). The Nexys A7-100T DMA Audio demo uses a similar approach to bring in .wav files to play back through headphones or a speaker, although i
  13. @Paul Chang I haven't managed to reproduce this yet. For what it's worth, I also use a Windows 10 system. Thanks for posting the log file. According to this Xilinx Forum thread, there may be some strange issues relating to the AXI SmartConnect that depend on system settings. I have a couple of ideas for things that we could try to work around it. 1. I've attached an archived version of the project, which I checked out on my machine. 2. If (1) doesn't work, it may be necessary to replace the AXI SmartConnect with an AXI Interconnect. This could get a bit complicated, an
  14. The material I referenced discusses how to recreate an HDF file from the sources. After this, using the demos in baremetal should only require updating the hardware specification for the SDK hardware platform to the new HDF in the SDK workspace in the SW submodule. Using them in Linux requires retargetting the petalinux project (the OS submodule) to the new HDF and rebuilding it (I am less clear on this process, but the Adding Zmod Support in Petalinux guide should cover the relevant commands) - this is only possible in Linux, due to the Petalinux installation requirements. The OOB is the
  15. With regards to this, the process is described in Workflow 5 of the digilent-vivado-scripts readme. In addition to these, the steps in the Eclypse Z7 Git Repo Documentation's Navigating and HW sections should be used after cloning, and before running any scripts. I am looking into getting these steps all in one place. -Arthur