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  1. Inclusion of the ps7_init and HDF file in the application project src folder (and the ps7_cortexa9_0 folder in the _today project) looks very strange to me. It also seems to have caused a lot of errors when I opened the workspace and built it on my system, so I am not sure if something strange happened when sharing the workspace. If this reflects what you have on your system, you could try just creating a new Hello World application project to confirm that the exported hardware is valid, and that you can program and communicate with your board. <-- This is what I would expect the application project to look like. (Error is a result of using sources from another HDMI demo with differently-named IPs)
  2. Needed to double check. Have you connected a serial terminal (Tera Term or whatever)? If so, what is being printed by the demo? For what it's worth, I've seen similar projects halt on "printf" statements before, depending on Vivado version and the board used. xil_printf generally works fine, but does not accept floats. Here's a diff of a fix for that issue. Could you zip and share your SDK workspace?
  3. Have you programmed the hardware and run the demo application in Xilinx SDK? Both the hardware and software must be running on the board to get an image.
  4. Looks like the board may be booting the out-of-box demo from QSPI flash. It is still possible to program it while this is happening, but you may still want to move the JP6 jumper to JTAG mode. -Arthur
  5. I believe that there is a bug in that particular version of the dvi2rgb decoder. A workaround would be to just set the TMDS clock range parameter to ">= 120 MHz". Alternatively, you could replace the core in the project's repo folder with the latest version of that IP, which has resolved that bug, found in this ZIP. Thanks, Arthur
  6. This error is likely related to the rgb2dvi IP. Please send a screenshot of its configuration (see below).
  7. Looks like the project was just missing constraints. I am unsure what the root cause of the problem is, but I managed to generate a bitstream. Download the attached XDC file and add it to your project. Thanks, Arthur Zybo-Z7-Master.xdc
  8. Hi @Dareamol Open the Zynq Processing Blocks's configuration wizard. Within this, there is a tab called "MIO Configuration". Expand the "I/O Peripherals" section and scroll down to "SPI 0" and "SPI 1". The checkboxes on these lines can be used to enable the modules. The "IO" dropdown can be used to select what pins the modules control. In the case of the Zybo Z7-10, these modules must be connected to EMIO, which connects the SPI interfaces to the Zynq's programmable logic. From there, you can make these interfaces external and connect them to whatever external pins through your constraint file/s. More potentially useful information can be found in this thread on the Xilinx forums. Thanks, Arthur
  9. Please use File -> Archive Project in Vivado to create a ZIP of the project. It should pick up dependencies outside of the project folder, in addition to the project folder itself. Unfortunately, projects (particularly those using create_project style scripts) are not easily portable between different versions of Vivado. As stated in the HDMI demo's wiki page, Vivado 2016.4 must be used to run the create_project script. The demo's release for 2018.2, found via the GitHub readme here, should at least be openable in any version of Vivado 2018.2 or newer, though problems may occur when not using that exact version. Thanks, Arthur
  10. Hi @johnsan1 As there is only one UART link between the PC and your board, you cannot use more than one instance of Tera Term. I am assuming you have a Vivado block design containing two Pmod AD2 IP cores. The provided SDK example code only configures and reads from one AD2. In order to view samples from both AD2's at the same time, you must edit the example code to configure and control both AD2s and print data from both out over the serial interface. A starting point would be to add a second device driver instance to the code by editing line 44 of the example code as follows: PmodAD2 myDevice_JA, myDevice_JD; Thanks, Arthur
  11. Hi @tekson I believe that this issue may be related to capitalization of the port names in the constraint file. This is easily correctable by comparing the [get_ports <name>] names in the XDC file to the port map in the block design's *_wrapper.v file, and editing the names in the XDC to match the wrapper. Both files can be found in the Sources / Hierarchy pane in Vivado. If you provide a link to the materials you are working from on our wiki or github, I should be able to correct the issue. Thanks, Arthur
  12. When using a Pmod IP core, only I2C Pmods have their pullups enabled, all others use neither by default. The resistors can be enabled by adding a constraint file to the project and entering a line something like the following: set_property PULLUP TRUE [get_ports ja_pin1_io] set_property PULLDOWN TRUE [get_ports ja_pin2_io] Using this method for the I2C Pmods might cause some issues, depending on how Vivado handles the constraint file order. Thanks, Arthur
  13. Hi @Dareamol It depends on the constraints used in your design. Internal pullups and pulldowns can be enabled by modifying the implemented design, or by modifying the constraint file/s. By default the pins have both pullups and pulldowns disabled. Thanks, Arthur
  14. Hi @aadgl DMA is fast enough. At least when there is little else using the DDR, Xilinx's AXI DMA IP can handle data rates significantly higher than your requirement (See the Performance section of its datasheet). I've only built projects with the AXI DMA from scratch on Zynq devices before, which do not use the MIG, so I'm not certain how to go about connecting the MIG to the DMA. I believe that there is at least one demo for the Nexys Video that could be used as reference. Getting it all set up for the first time can be tricky. If you have questions, we're happy to help. Some general thoughts: Running all of the AXI/AXIS interfaces off of the same clock makes everything a lot easier. Grouping your data into 32 bit words before streaming it to the DMA is also helpful. Make sure that Microblaze and your IP are working on the same size of packet. The AXI DMA needs to be told by Microblaze how many words it is expecting, and the IP needs to provide a tlast signal at the expected time. When trying to access DMA'd data from Microblaze, that data must be invalidated in the cache.
  15. Welcome to the forum, @vahid There is a lot of good information in this thread on the Xilinx forums. I've attached a Vivado 2019.1 project with a very simple VHDL testbench. Thanks, Arthur