# tip.can19

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1. ## What is CYINIT and it's difference with CI in CARRY4 block?

Hi @JColvin Thank you! I have now understanding of CYINIT. Regards,
2. ## What is CYINIT and it's difference with CI in CARRY4 block?

Hi, I was looking to know what CYINIT is in CARRY4 block and it's role? I assume the CI is the carry in from previous cascade, but not sure. Any idea on this? I use Xilinx 7-series device in Vivado 2019.1, we can refer UG953 (page.290) for CARRY4 block. Thank you,
3. ## What would be difference between clock latency and propagation delay?

Thank you very much @zygot !!! @zygot You explanation is the best! I got very good understanding of this concept from your deep explanation. Thanks so much again.. Really appreciate your help! Kind Regards Tip
4. ## How to understand -edge option if first edge of generated clock is falling edge?

Hi JColvin, Thanks for your inputs and reply. Really appreciate it. As you correctly pointed out, as per the -edge {rise,fall,rise and so on..}, what we think is edge {5,7,11} is period of generated clock with 2ns of positive and 3ns of negative period (5ns total with first rise outside the master clock period) and hence from 10th edge the waveform should repeat itself to maintain the clock. Thus from 10th edge to next edge i.e. 11th edge (or 1st edge since clock is repeated) the engine will automatically infer positve period and auto infer falling edge at 2 (not ns but edge). I coul
5. ## How to understand -edge option if first edge of generated clock is falling edge?

i think i misunderstand the diagram with edges. I suppose the 11th edge is nothing but first edge, so from 10 to 11th edge is equal to high period (1 step/1ns) and then 1 to 2nd edge (1ns) as another step which makes positve 2ns, so the fall is at edge 2 and not 3. I hope this understanding is correct.
6. ## How to understand -edge option if first edge of generated clock is falling edge?

I am trying to understand the waveform created by create_generated_clock with -edge option. Suppose I have master clock as create_clock 2 [get_ports DCLK] like PFA - master_clock.png I do create_generated_clock -name G3CLK -edges {5 7 10} -source DCLK [get_pins UAND0/Z] Assuming needed is first edge of generated clock is falling edge, it is inferred at 1ns (or 2) automatically and why not at 3? Why would that be? PFA generated_clock.png Thanks
7. ## What would be difference between clock latency and propagation delay?

Thanks for expanation! This helps a lot! @xc6lx45.
8. ## What would be difference between clock latency and propagation delay?

I believe the clock latency is the total time it takes from the clock source to an end point. PFA Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below. PFA So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture? Thanks Tip