Bilal29

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  1. Bilal29

    Nexys Video XADC

    1. How we can provide analog input to dedicated VP/VN. Only JXADC port given for auxiliary inputs (Four Inputs). 2. My XADC auxillary inputs is not working but on chip sensors are working fine. I am giving analog input in between 0 V to 1.0 V to JXADC (Aux input channel 0) from external Power supply but ADC is reading constant value.
  2. In this mode results are stored automatically in status register like 00h (temperature), etc. No need to select channel for conversation and configure once sets initially in IP core. I know default mode monitors on chip sensors only. My question is that how you can read status register without selecting channel (01h, 02h,06h…)? We have to write address through drp Daddr register and enabling den and dwe register and then read dout by disabling dwe and enabling den again. When drdy==1 read dout ?
  3. Ip core data is not present. Dont what they have initialized with. Like: XADC #( .INIT_40(16'h9000), // config reg 0 .INIT_41(16'h2fff), // config reg 1 .INIT_42(16'h0800), // config reg 2 .INIT_48(16'h0200), // Sequencer channel selection .INIT_49(16'h0000), // Sequencer channel selection .INIT_4A(16'h0000), // Sequencer Average selection .INIT_4B(16'h0000), // Sequencer Average selection .INIT_4C(16'h0000), // Sequencer Bipolar selection .INIT_4D(16'h0000), // Sequencer Bipolar selection .INIT_4E(16'h0000), // Sequencer Acq time selection .INIT_4F(16'h0000), // Sequencer Acq time selection .INIT_50(16'hb5ed), // Temp alarm trigger .INIT_51(16'h57e4), // Vccint upper alarm limit .INIT_52(16'ha147), // Vccaux upper alarm limit .INIT_53(16'hca33), // Temp alarm OT upper .INIT_54(16'ha93a), // Temp alarm reset .INIT_55(16'h52c6), // Vccint lower alarm limit .INIT_56(16'h9555), // Vccaux lower alarm limit .INIT_57(16'hae4e), // Temp alarm OT reset .INIT_58(16'h5999), // VBRAM upper alarm limit .INIT_5C(16'h5111), // VBRAM lower alarm limit .SIM_DEVICE("7SERIES"), .SIM_MONITOR_FILE("design.txt") ) Only below mentioned code is present with top module. It is incomplete. Ug 480 include all code but it is not working. xadc_wiz_0 XADC ( .daddr_in(xadc_addr), .dclk_in(CLK100MHZ), .den_in(enable), .di_in(), .dwe_in(), .busy_out(), .vauxp0(xa_p[1]), .vauxn0(xa_n[1]), .vauxp1(xa_p[0]), .vauxn1(xa_n[0]), .vauxp8(xa_p[2]), .vauxn8(xa_n[2]), .vauxp9(xa_p[3]), .vauxn9(xa_n[3]), .do_out(xadc_data), .eoc_out(enable), .channel_out(), .drdy_out(ready) );
  4. Can you please share complete verilog top module code of ADC. Verilog code will be same whether we use ISE or vivado !
  5. 1. I am using nexys video to read analog values but output is showing zero in UART terminal. I have used verilog code mentioned in UG 480 v1.10.1. I am using ISE 14.4 and XADC IP core . I did a slight change in code by setting clk divide to 8 instead of 4 since nexys video has 100 Mhz clock. Secondly, i have enable VCCINT channel only. 2. Secondly in automatic channel sequencer we have to wait for drdy only and read data from do_drp of the selected channel ? No need to write data initially through DRP since it is initialized in IP core ? 3. ADC top module is shown below and IP core code is attached: `timescale 1ns / 1ps module ADC_TOP( input clk, input arst_n, output reg [15:0] MEASURED_VCCINT ); reg [6:0] daddr; reg [1:0] den_reg; reg [15:0] di_drp; reg [1:0] dwe_reg; wire [15:0] do_drp; wire drdy; reg [7:0] state; parameter init_read = 8'h00, read_waitdrdy = 8'h01, write_waitdrdy = 8'h03, read_reg01 = 8'h06, reg01_waitdrdy = 8'h07; ADC_IP_Core UUT_ADC_IP ( .DADDR_IN(daddr), .DCLK_IN(clk), .DEN_IN(den_reg[0]), .DI_IN(di_drp), .DWE_IN(dwe_reg[0]), .RESET_IN(arst_n), .BUSY_OUT(busy), .CHANNEL_OUT(), .DO_OUT(do_drp), .DRDY_OUT(drdy), .EOC_OUT(), .EOS_OUT(), .ALARM_OUT(), .VP_IN(), .VN_IN() ); always @ (posedge clk or negedge arst_n) if (arst_n) begin state <= init_read; den_reg <= 2'h0; dwe_reg <= 2'h0; di_drp <= 16'h0000; end else case (state) init_read : if (busy == 0 ) state <= read_reg01; read_reg01 : begin daddr <= 7'h01; den_reg <= 2'h2; // performing read state <=reg01_waitdrdy; end reg01_waitdrdy : if (drdy ==1) begin MEASURED_VCCINT <= do_drp; state <=read_reg01; daddr <= 7'h01; end else begin den_reg <= { 1'b0, den_reg[1] } ; dwe_reg <= { 1'b0, dwe_reg[1] } ; state <= state; end endcase endmodule ADC_IP_Core.v
  6. Bilal29

    Nexys Video

    hi, jpeyron It seems that GPIO demo is loaded. I was little worried when i saw temperature increasing. so i just powered off to avoid further damage. But i seems fine as per suggestion.
  7. Bilal29

    Nexys Video

    By default which program is loaded from flash. If DDR is running then what will be the maximum temperature it will show on display ? Is there any UCF file of board. Only XDC file is available.
  8. Bilal29

    Nexys Video

    I recently purchased nexys video board and after powering ON in default conditioned, i noticed FPGA temperature is increasing (Temperature is displayed on Screen). When it reaches 47 degree c, i disconnected its power. Is this a problem or it is fine ? Secondly, by default which program is loaded in it ? and by default what i can check without changing code.