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  1. Hi JColvin, Thank-you for your reply. The 12 pins I am referring are listed at the as the last items in the Zybo .xdc file. They are seen on ZyboZ7_schematic page 11/14 as part of BANK 13. V10 for example is listed on page 11/14 as V10 (IO_L21N_T3_DQS_13) and netic19_v10 in the .xdc file, but don't see any connectors related to V10 on the ZyboZ7_20 board. Can these be accessed? Thanks
  2. I have two questions concerning my Zybo Z7-20 board. Question 1: According to the Zybo-Z7 2018 reference manual, the MIPI port has a 15 pin connector. Page 28, reference manual shows the connector labels as: Pin # Function Zybo Z7 Connection Details 1 GND GND 2 MIPI CSI-2 Lane 0 (-) Terminated and connected to 2 FPGA pins asdescribed in XAPP894 3 MIPI CSI-2 Lane 0 (+) Terminated and connected to 2 FPGA pins as described in XAPP894 4 GND GND 5 MIPI
  3. Yep, used the same cable when testing the Nexys 4 DDR and CmodA7. Tried the cable for my Analog Discovery 2 and had the same results. Hooked up my Zybo and it works too. Right now I am limping with the Zybo, but since the Zybo has been modified I would much rather go back to the Nexyx 4 DDR.
  4. For several months I have been using a Nexys4 DDR board on my Linux system for Vivado 2019.1 software development. A couple of days ago it Vivado would suddenly not recognize the board. A quick check in /dev/ttyUSBx shows the board did not register with the Linux OS. After deleting the rules file, I reinstalled the VIvado drivers. Still didn't register with /dev/ttyUSBx. Several cold reboots; nada. (Can't find the Digilent rules files) Then I tried using a Cmod A7 on the same Linux system and it worked! Then I connected the Nexys4 board and two other Linux systems. one Vivado 2019.1 and t
  5. Thanks, I think it will be easier just to transfer to a Genesys-2 board. Eventually we'll have to deal with some parallel data and the idea of 100+ lines is appealing.
  6. I can't thank-you enough for this very informative answer, I really appreciate your taking the time to answer my question. "What kind of IO do you want?" The type of IO we are using is simply an array of SPI and UART connections. I think we are up to 14 independent SPI connections and 1 UART connection. Due to the nature of the design we need to keep the connection independent and would like to avoid the overhead of a mux. We started out building this prototype using a Zybo Z7, but are now at a point where there a simply not enough connections. We have jumpered a couple of buttons, t
  7. I have an I/0 limited application and looking through the Digilent catalog I find several boards with FMC/HPC connectors and am wondering if the pins can be used as general I/O ports. For example, the Genesys-2 board. If so, can you recommend a mezzanine card to communicate signals to and from the FMC connector? Cheers,
  8. rzsmi

    Pmod wifi SDK problem

    FYI, tried Linux as alternative and ran into a completely different set of problems. The make file had errors.
  9. rzsmi

    Pmod wifi SDK problem

    I am wondering if there is any update to this problem? Your link suggests the solution is to go Windows 7, which is not a viable solution. According to the global-build.log, 76 In file included from ./DEIPcK/utility/deIP.h:409:0, 77 from ../../../include/DEIPcK.h:64, 78 from DEIPcK/DEIPcK.cpp:54: 79 ./DEIPcK/utility/DHCP.h:216:25: error: flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' 80 uint8_t options[]; // variable lenght options ends with the end opiton of 0xFF 88 In file included from
  10. More newbe questions. I appreciate all of your patience and help, and the saga continues. I have purchased a PmodOLEDrgb to explore AXI bus and the Pmod ports on your boards. To this end I am following the instructions on the Youtube video: https://www.youtube.com/watch?v=kb2bOUv77Qc Titled: Show and Tell Ep. 14 - Plug and Play Pmod IPs on Zybo and Arty. I have successfully completed the instructions using a CmodA7-15 with a Microblaze. I am now attempting the same feat with my Zybo-Z7- 20. Following the video, as best I can, I can program the Zybo using the example in the vi
  11. https://reference.digilentinc.com/vivado/getting-started-with-ipi/start Step 1.5 clearly shows the procedure was leveled at a zybo. Step 4.2 the reader is given a choice between a Zynq or Microblaze. In my attempts at the procedure, I was able to successfully use the Zynq recipe, but was unable to get the Microblaze to work. Cheers,
  12. To be frank, I wanted to try the MicroBlaze on my Zybo Z7 only because the getting started web page said it could be done and thought it would be instructive. The real goal is to implement the Microblaze on a Cmod-A7. I must agree the Zybo MicroBlaze is not trivial... Having said that, there is a recipe on the a fore mentioned Getting Started web page that says it can be done and here's how to do it. I mention this because as an unsuspecting newbie I tried for a few days to get it to work. Many thanks for your answer confirming the Microblaze configuration task is best left to non-zy
  13. I am following the steps outlined in https://reference.digilentinc.com/vivado/getting-started-with-ipi/start I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor. The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest. [DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/
  14. I am going through the Zynq Book Tutorial, version 1.3 April 2014. It seems the Zynqbook and Zynqbook Tutorial are leveled at Vivado 2014.x Zedboard and I have Vivado 2017.2 and Zybo Z4-20 board. Following example 1.B for the Zedboard, the tutorial states on page 15, "Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO." Then a dialog box labeled "Run Connection Automation" will appear. In my version of VIvado or Zybo constraints I don't get this popup window or a selection the looks like /axi_gpio_0/GPIO a