rzsmi

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About rzsmi

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  1. More newbe questions. I appreciate all of your patience and help, and the saga continues. I have purchased a PmodOLEDrgb to explore AXI bus and the Pmod ports on your boards. To this end I am following the instructions on the Youtube video: https://www.youtube.com/watch?v=kb2bOUv77Qc Titled: Show and Tell Ep. 14 - Plug and Play Pmod IPs on Zybo and Arty. I have successfully completed the instructions using a CmodA7-15 with a Microblaze. I am now attempting the same feat with my Zybo-Z7- 20. Following the video, as best I can, I can program the Zybo using the example in the video, but when I run as:(debug mode), the program just doesn't work. The same behavior occurs using various JP5 jumper setting. With the JP5 in the QPSI setting, the program seems to run, but jumps to the default program before displaying anything on the screen. Looking thru the console messages I see: Description Resource Path Location Type comparison between signed and unsigned integer expressions [-Wsign-compare] PmodOLEDrgb_selftest.c /ZyboPmodOLD_v1_bsp/ps7_cortexa9_0/libsrc/PmodOLEDrgb_v1_0/src\ line 57 C/C++ Problem Well this can cause problems when comparing results: http://subethasoftware.com/2017/12/01/c-warning-comparison-between-signed-and-unsigned-integer-expressions-wsign-compare/ and I decided to print out these values just for fun to see these values at line 55 in the PmodOLEDrgb_selftest.c file. xil_printf("PMODOLEDRGB_mReadReg = %d\n", PMODOLEDRGB_mReadReg (baseaddr, read_loop_index*4)); xil_printf("read_loop_index+1 %d\n", (read_loop_index+1)*READ_WRITE_MUL_FACTOR); altho it compiled, I got the following warning: Description Resource Path Location Type ...this statement, but the latter is misleadingly indented as if it were guarded by the 'for' PmodOLEDrgb_selftest.c /ZyboPmodOLD_v1_bsp/ps7_cortexa9_0/libsrc/PmodOLEDrgb_v1_0/src line 55 C/C++ Problem I didn't realize the were guardians of the 'for' statement. Sounds like a good plot for a movie. I have some questions about all of this. 1. Where does the xil_print statement put the output? Ran the newly compiled program and can find the values anywhere. 2. The console message disappear after it compiles. Where can I read the console messages after they are gone from the screen? 3. Is there any insight to getting it working on the Zybo. I include my block design. Again many thanks for your help. Cheers,
  2. https://reference.digilentinc.com/vivado/getting-started-with-ipi/start Step 1.5 clearly shows the procedure was leveled at a zybo. Step 4.2 the reader is given a choice between a Zynq or Microblaze. In my attempts at the procedure, I was able to successfully use the Zynq recipe, but was unable to get the Microblaze to work. Cheers,
  3. To be frank, I wanted to try the MicroBlaze on my Zybo Z7 only because the getting started web page said it could be done and thought it would be instructive. The real goal is to implement the Microblaze on a Cmod-A7. I must agree the Zybo MicroBlaze is not trivial... Having said that, there is a recipe on the a fore mentioned Getting Started web page that says it can be done and here's how to do it. I mention this because as an unsuspecting newbie I tried for a few days to get it to work. Many thanks for your answer confirming the Microblaze configuration task is best left to non-zynq boards. Cheers.
  4. I am following the steps outlined in https://reference.digilentinc.com/vivado/getting-started-with-ipi/start I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor. The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest. [DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. [DRC UCIO-1] Unconstrained Logical Port: 2 out of 11 logical ports have no user assigned specific location constraint (LOC). I have attached the full error and block design. ---- I wish to add a couple of comments regarding Vivado. In my installation on two different computers; in step 5.2 when defining the Top Module, the 5.2 recipe does not work for me on these two Windows installations. However, if one exits Vivado and restarts Vivado, the top module magically appears. However, if one starts Vivado from its desktop icon, Vivado get confused as to what is its project name. If one starts Vivado at this point from the file name in the project directory (ProjectName.xpr) the problem goes away. (See attachment VivadoProjName.JPG, project name is GettingStarted_3) GettingStarted_error.txt
  5. I am going through the Zynq Book Tutorial, version 1.3 April 2014. It seems the Zynqbook and Zynqbook Tutorial are leveled at Vivado 2014.x Zedboard and I have Vivado 2017.2 and Zybo Z4-20 board. Following example 1.B for the Zedboard, the tutorial states on page 15, "Click Run Connection Automation from the Designer Automation message at the top of the Diagram window and select /axi_gpio_0/GPIO." Then a dialog box labeled "Run Connection Automation" will appear. In my version of VIvado or Zybo constraints I don't get this popup window or a selection the looks like /axi_gpio_0/GPIO and now am at a loss on how to connect the AXI GPIO and LEDs. Is there a newer version of this book that includes the Zybo Z7-20 series? Thanks in advance.
  6. I am getting starting with Vivado_HLS 2018.2 and the zyboZ7-20 board. When attempting to create a project I find no default setting for the zyboZ7-20 board in the Vivado HLS "Part Selection". What is the recipe for giving the zyboZ7-20 board information to Vivado HLS? I see there are some examples using Vivado, but none using Vivado HLS. Being new at this, step-by-step would be very helpful. Thanks
  7. Newbie here. I purchased a Digilent Zybo Z7 development board that came with a OEM SDSoc-Zynq license. I downloaded SDxIDE 2018.2 software, registered the license that came with the Zybo board with Xilinx, and checked all the boxes that I could on which applications to license. When I start the Xilinx SDxIDE application I get a message: "The SDx project flow requires an SDSoC or SDAccel 'License Manager' to acquire license." Clicking and following a couple of links I find the "Product Licensing" page says that I have a "OEM SDSoC-Zynq Development Voucher" with 1 active seat. I realize the is probably a xilinx issue and have asked the question on their board, (with reply at this point). I am confused and wondering what entitlements are included with the Developer Voucher?