• Content Count

  • Joined

  • Last visited

About Pavel_47

  • Rank
    Frequent Visitor

Profile Information

  • Gender
  • Location
    : Lausanne, Switzerland

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Hi JColvin, I joined Arty S7 Workshop, organized by "Element 14". It's based on Arty 7. In his example the speaker uses MicroBlaze. Since I don't have an Arty card, I thought I could use my Zybo Z7 card. So there is no way to connect UART to PL? Thanks, Pavel.
  2. Hello, Why USB UART isn't present in Zybo-Z7 interfaces (please, see screenshot) ? Another question: does exist a special button for reset ? Thanks, Sincerely, Pavel
  3. I'm not sure that I properly understood your explanation, but indeed there is some relation between LD2 behavior and capture duration. For example in this example with base 20ms/div (i.e. capture 200ms) and higher, the LD2 flashes; with 10ms/div and lower it's ON continuously
  4. Hi Attila, I've observed two types of behavior on LD2: white continuous white flashing Does exist a document where this is specified ? Thanks.
  5. Hello, LD2 flashes white on Digital Discovery. What does it mean ? Thanks.
  6. Pavel_47

    JTAG-HS2 under linux

    Hello, Can I use JTAG-HS2 under Linux and in particular with Vivado ? If yes, how properly install it ? Thanks.
  7. Yes. It works ! I've compared the output of my program with the "golden" result, obtained from the execution of the fpga -config-status instruction. And it's the same !!! Thanks.
  8. Hi, Yes! Probably have a reason. After a closer look to the "golden waveforms" I see that it doesn't correspond to 100% to the sequence,described in the table 6-2 of UG470. Here is the beginning of the "golden sequence" picked with LeCroy: I've divided this beginning part in 6 phases: phase 0: don't understand what is it for phase 1: put TAP controller in TLR state (because with TMS = 1 five consecutive pulses are sufficient to return to TLR from whatever state) phase 2: put TAP controller in Shift-IR state phase 3: shift CFG_IN (000101) instruc
  9. Hi, I'm afraid I didn't properly understand what you mean. If I push BYPASS code into IR, how it will help me to resolve the problem ? In the "golden sequence" (i.e. fpga -config-status) I don't see. One more observation: the execution of dadutil enum -t produces the following: No devices found. So, if my comprehension is correct, digilent utility dadutil doesn't see Xilinx chips? I've tried it on two boards: XC706 (Zynq-7045) and KCU105 (Kintex Ultrascale) and the result is the same. BR.
  10. Thanks for suggestion Zygot. Xilinx forum as well as Xilinx official support were already tried ... no any result, so I should search for a solution myself. Sincerely Pavel
  11. Hi Gra, Thanks for feedback. No, partial configuration isn't my primer interest, but rather ... as I sayed below - frame-based configuration, which is not the same thing.
  12. Hi Zygot, The goal is to perform "customized" configuring of FPGA ... e.g. frame-based. It means one frame or several frames (not whole bitstream !) are read, then modified in certain way, and then rewritten back in the FPGA. To my knowledge there is no tools that provide such capability. Sincerely. Pavel.
  13. Thanks JColvin, Yes, you were right - I was wrong trying to pass CFG_IN instruction that way. Since my code has undergone many changes. Here how it looks now: Declaration part: HIF hif; char jtag_version[20]; BYTE reset_JTAG_tms[] = { 0x1F }; BYTE move_Shift_IR_tms[] = { 0x0C }; BYTE shift_IR_tmstdi[] = { 0x11, 0x08 }; BYTE move_Shift_DR_tms[] = { 0x03 }; BYTE shift_Packets[] = { 0x55, 0x99, 0xAA, 0x66, 0x04, 0x00, 0x00, 0x00, 0x14, 0x00, 0x07, 0x80, 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00 }; BYTE shift_Packets_last[] = { 0x00, 0x80 }; BYTE move_shift_IR1[] = { 0x07 }; BYTE shif
  14. Yes, it was exactly the case ! The time laps between 2 consequent function calls are so long (why ?) that the 2nd call occurs outside of the time scope, covered by LeCroy software. I've modified a little my code in order to follow step-by-step the JTAG sequence: So, executing each instruction separately, I can control what is going on at JTAG lines.
  15. Hello Zygot, Probably I was misunderstood. I'm not interested in USB aspects of JTAG-SMT2™ module. I consider that the instruction I send over USB cable are properly translated in sequences on JTAG lines. And it's JTAG aspect that I'm interested in. Unfortunately I didn't find any other approach to communicated with FPGA over JTAG. Well ... there is some Tcl instructions in Vivado and SDK, but it's even worth ... while Digilent provide some documentation on Adept software with a couple of examples, Xilinx doesn't provide any examples. Sincerely, Pavel.