xzsawq21

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  1. I really need your help. my time is very restricted this is my sources could you please check it? 1-the block design: I added the below ports in my AXI core: // Users to add ports here output [3:0] out_mux, output a, b, c, d, e, f, g, dp, I have added my module as following: in my AXI core ( especially take a look from clk_100MHz to m0) is it right? // Add user logic here my_7seg_hdl U1( .clk_100MHz(S_AXI_ACLK), .res(S_AXI_ARESETN), .h1(slv_reg0[15:12]), .h0(slv_reg0[11:8]), .m1(slv_reg0[7:4]), .m0(slv_reg0[3:0]), .a(a), .b(b), .c(c), .d(d), .e(e), .f(f), .g(g), .dp(dp), .out_mux(out_mux)); // User logic ends my module: module my_7seg_hdl (clk_100MHz, res, h1, h0, m1, m0, a, b, c, d, e, f, g, dp, out_mux); input clk_100MHz; input res; input [3:0] h1, h0, m1, m0; output a, b, c, d, e, f, g, dp; output [3:0] out_mux; reg [6:0] sseg; reg [3:0] out_mux_temp; reg reg_dp; reg [19:0] refresh_counter; wire [1:0] LED_activating_counter; always @(posedge clk_100MHz or posedge res) begin if(res==1) refresh_counter <= 0; else refresh_counter <= refresh_counter + 1; end assign LED_activating_counter = refresh_counter[19:18]; always @ (*) begin case(LED_activating_counter) 2'b00 : begin sseg = m0; out_mux_temp = 4'b1110; end 2'b01: begin sseg = m1; out_mux_temp = 4'b1101; end 2'b10: begin sseg = h0; out_mux_temp = 4'b1011; end 2'b11: begin sseg = h1; out_mux_temp = 4'b0111; end endcase end assign out_mux = out_mux_temp; reg [6:0] sseg_temp; always @ (*) begin case(sseg) 4'd0 : sseg_temp = 7'b1000000; 4'd1 : sseg_temp = 7'b1111001; 4'd2 : sseg_temp = 7'b0100100; 4'd3 : sseg_temp = 7'b0110000; 4'd4 : sseg_temp = 7'b0011001; 4'd5 : sseg_temp = 7'b0010010; 4'd6 : sseg_temp = 7'b0000010; 4'd7 : sseg_temp = 7'b1111000; 4'd8 : sseg_temp = 7'b0000000; 4'd9 : sseg_temp = 7'b0010000; default : sseg_temp = 7'b0111111; //dash endcase end assign {g, f, e, d, c, b, a} = sseg_temp; assign dp = reg_dp; endmodule the SDK code to send a number 2314 (h1=2 and h0=3 and m1=1 and m0=4): #include "stdio.h" //printf #include "platform.h" #include "xbasic_types.h" //#include "xil_types.h" #include "xparameters.h" #include "xil_printf.h" //xin_printf #include "xil_io.h" //xil_in32 , xil_out32 #include "sleep.h" //sleep() u32 *BASEADDR_p = (u32 *)XPAR_AXI_MY_7SEG_0_S00_AXI_BASEADDR; int main() { init_platform(); xil_printf("Project Started\n\r"); *(BASEADDR_p+0)=0x2314; //Write to register 0, Actually h1=2 and h0=3 and m1=1 and m0=4 sleep(2); cleanup_platform(); return 0; }
  2. what difference is between adding a module and creating an AXI Custom IP? for these days I'm coding to learn creating AXI IP core but very soon I should crate some custom IP to work with a high speed ADC and DAC to save some big data on DDR3.
  3. Dear I'm newbie to AXI core. I have reviewed all your replies and I have learned lots of things. Actually I'm puzzled when I want to add some Verilog code under "Add User Logic here" section. for example I set slv_reg0 with a number in the SDK. (I have used Xil_Out32(add,0x2311)) the first 16 bits of slv_reg0 is dedicated to the Hours and second 16 bits of slv_reg0 is dedicated to the Minuets after that I will convert the HH and MM to a proper 7 seg code. (using a lookup) now how should I write a module under "Add User Logic here"? Actually in pure Verilog coding it's easy but here I'm very puzzled! could you please help me? please.
  4. Hello could you please send me a report of HD2 and HD3 of "Analog Discovery 2" over frequency axis like the below pic? https://drive.google.com/open?id=1qIUkIX3uahRgPyE8tQPFONsWItei319b HD2=second harmonic distortion HD2=third harmonic distortion if you want I can give you my email address. Thanks