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  1. I really need your help. my time is very restricted this is my sources could you please check it? 1-the block design: I added the below ports in my AXI core: // Users to add ports here output [3:0] out_mux, output a, b, c, d, e, f, g, dp, I have added my module as following: in my AXI core ( especially take a look from clk_100MHz to m0) is it right? // Add user logic here my_7seg_hdl U1( .clk_100MHz(S_AXI_ACLK), .res(S_AXI_ARESETN), .h1(slv_reg0[15:12]), .h0(slv_reg0[11:8]), .m1(slv_reg0[7:4]), .m0(slv_reg0[3
  2. what difference is between adding a module and creating an AXI Custom IP? for these days I'm coding to learn creating AXI IP core but very soon I should crate some custom IP to work with a high speed ADC and DAC to save some big data on DDR3.
  3. Dear I'm newbie to AXI core. I have reviewed all your replies and I have learned lots of things. Actually I'm puzzled when I want to add some Verilog code under "Add User Logic here" section. for example I set slv_reg0 with a number in the SDK. (I have used Xil_Out32(add,0x2311)) the first 16 bits of slv_reg0 is dedicated to the Hours and second 16 bits of slv_reg0 is dedicated to the Minuets after that I will convert the HH and MM to a proper 7 seg code. (using a lookup) now how should I write a module under "Add User Logic here"? Actually in pure Veri
  4. Hello could you please send me a report of HD2 and HD3 of "Analog Discovery 2" over frequency axis like the below pic? https://drive.google.com/open?id=1qIUkIX3uahRgPyE8tQPFONsWItei319b HD2=second harmonic distortion HD2=third harmonic distortion if you want I can give you my email address. Thanks