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  1. Well, the library is still in the works, but I've done a little testing to see how the chip outputs its readings. Regarding just the raw data value you will get from a reading, the device seems to set the minimum reading (0x00 or 0) at the bottom of the range determined by the configuration settings and just outputs the data linearly. So your midpoint value would be 0x800000. Now the actual voltage range that is readable by the device is slightly less straight forward. For an example, lets say you had the device configured for pseudo-differential inputs, bipolar mode, with a gain of
  2. Hey @SkeptoLogic, Testing the configuration and mode settings you provided, I am getting similar outputs to what you stated you were reading (if I am understanding your post correctly). I am currently working on a library for the pmodAD5, so as I finish it up I should be able to give you some more definitive answers. In my recent experience with the AD5 though, and having read through the datasheet as well, I too have been having some difficulty deciphering differences between certain actual outputs and my expectations. Sorry for not having a whole lot of info for you at the moment,
  3. Hey yassin, I haven't done much with petalinux in the past year, but unless there has been some dramatic changes petalinux itself has to be run in one of the supported Linux environments. So if you mean that you don't have a native Linux machine I would suggest setting up a Linux virtual machine and working with petalinux from there. I am not sure if there is a specific Sobel filter project you are referring to, but as for creating an image with petalinux that includes a Sobel filter, you could approach this a couple ways. Adding a filter block in Vivado to a block design would let y
  4. Hey Dig2, So to your questions, the negative (alligator clip) of the BNC probe should not be connected arbitrarily, since it could lead to either erroneous measurements at best or damage to your devices at worst. A way I try to think about it is to ask what voltage do you want to measure? For instance, if you are measuring an AC output signal that you expect to swing between +/- 12V, you would not want to connect your reference point (alligator clip) to a voltage other 0V. If you connected your reference to -3V hypothetically, once the output signal reached its max you would actually get
  5. Hey Brett, I'm glad you were able to find a solution to the problem. Thank you for sharing that information, we will see about getting that updated as soon as possible. Regards, Nate
  6. Hey Axe, There may be a quick solution that jumps out from those screen shots, but it's not readily apparent to me. Can you provide a link to the specific project you are following? If I can create the project or recreate the issue you are having hopefully we can find you a solution quickly. -Nate
  7. Hey Rohit, The USB host functionality on the Zybo runs between the multiplexed IO at the ARM processor to an IC at the USB OTG port. The communication between this PHY and the processor is not something that I would recommend trying to develop yourself. The fastest way to getting peripherals interfaced with the board would be to run an embedded Linux image on it, for which there already exists drivers that would handle communication with various USB peripheral devices (something through PetaLinux would be quick to implement). If, however, you are trying to bring in an existing design
  8. Hey btb4198, The silk screen is a bit cramped and the header is one solid piece, so it is a bit hard to tell what's what. So the top two pins of that header are indicated as J6 and they do provide 5V. Similarly, the two bottom pins of the header are tied to ground and are marked as J15, so the second to last row are in fact pin 52 and 53 as you indicated. The pins in the rest of the header are split in two schematically. Header J8 includes the lower set of pins (from 38 to 53) and header J9 includes the upper set of pins (from 22 to 37). I hope this helps! -Nate
  9. I think for this example it might be helpful to frame what it is that is going on with your code. I am not sure this is correct, but I am assuming you are worried about a 'false' reset, meaning that the reset signal x1 is still high when the clock triggers the block. You can add another variable in your reset condition that indicates if x1 has been de-asserted, 'AND'ing those two signals together. This is just a suggestion though if you want to keep the design asynchronous, and I would encourage you as well to consider using synchronous resets if you can. -Nate
  10. Hey Can, I'd say your best bet would be to use the MPLAB X IDE for programming the Cerebot. It'll require a bit more work (determining register configurations and such) but you'll be able to program it with that. MPIDE would be more convenient if you just wanted to run a demo and tweak it a little, however the Cerebot will need to have a boot loader installed in order for you to program it with MPIDE. The boot loader is loaded during manufacturing for the successor to the Cerebot 32mx4 (the chipKIT MX4 Pro), however I am not certain if the Cerebot is compatible with the boot loader f
  11. Hey jcdammeyer, Welcome to the forum, and it's good to hear you are enjoying your Analog Discovery 2! To your question, I believe the calibration routine is not intended to be run with 10X probes connected to the AD2 (the last time I ran it the prompts were for direct connections between various channels of the AD2). We were able to replicate the issue you are having. With both probes set to 10x (for your bench scope and the AD2) as you mentioned is when the erroneous reading occurs, however it only appears to be an issue with that case and not when either probe is set to 1x (at
  12. Hey Beamer, Sounds like a pretty cool project you're working on! I have spoken to one of our engineers for some clarification on a couple of your questions. So to answer your questions: The short answer is no, unfortunately. There may be some type of example project in the future, but at the moment I am not aware of any that will be available soon. As for simultaneous communication with SPI and JTAG, this specific module does not support that. I have been told that we do have a chip on certain products that is capable of supporting both simultaneously (on the Nexys Video for i
  13. Hey Mehdim, There is an Instructable that is being written right now for implementing the Linux BD from the Digilent repo on the Zybo. I'll include the link in this thread for you once it is up. We are still at a stage where we are planning out our PetaLinux support material, but more will be coming soon! Regards, Nate
  14. Hey David, The USB OTG port is accessible through the processing system and not the FPGA portion of the Zynq chip, which is why you did not find anything for it in the .xdc file. You'll need to implement a Zynq block into a block design to make the processing system peripherals available for usage (USB-OTG, ethernet....possibly another). I'm not sure what functionality you need with your project, but there is a brief intro guide for the Zybo that we have. It does not use any peripherals, but it can serve to give you some insight into how you can leverage the processing system of the Zynq
  15. Hey Dakefeng, There is a way that this can be done in Linux. There is a utility called 'device tree compiler' that can compile .dts files into .dtb and vice versa. Xilinx has a wiki page that talks about this and its usage a little bit. I'm sure a quick search could also find you some more detailed information about it, but it is possible to do! -Nate