guantamanera

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  1. Thanks that works. I renamed it to be CLK100MHZ and LED in the verilog file as it shows in the constrains file. I blame this one on digilent since they don't mention this at all in their tutorial and also blame myself for not using my imagination 1 bit. Well it was long and tiring setting up the environment just to get started with the blinky tutorial. Hopefully things will not be so hard from here. Thank you kwilber. guantamanera
  2. Hello all, I bought the nexys 4 DDR, and since I am new I started with the basic tutorial blinky. Everything goes well until I get to step 8. "Synthesis, Implementation, and Bitstream Generation" The Synthesis ran successfully, and where it fails is at the bitstream generation. Since the Synthesis was completed I am assuming is not the verilog code, and is just some setting that I need to complete. The log gives the following error: ERROR: [DRC NSTD-1] Unspecified I/O Standard: 2 out of 2 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned spe