donwazonesko

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Everything posted by donwazonesko

  1. All this time i had answer on a plate. I've gone through few guides/forums/datasheet and i did not check the schematic. The answer is 1nF - if anyone is wondering. Best Regards, Michael
  2. Hello! I've nearly finished my project in which I use Basys3 board. Now I need to attach capacitors to lower the noices. What is the best capacity for that? Best regards, Michael
  3. Dear @jpeyron Could you please tell me if you attached capacitor C33 - C36 to your board (while working on Nexys 4 DDR Spectral Sources Demo? If yes, what capacity have you used? I need to lower the noice..
  4. Hello! I've finished my project reciving data from xadc and send it via UART to computer and now i want to create testbench using VHDL to simulate analog signal to XADC port's of my Basys3 board and test all of the components inside. I've found few VERILOG files and tutorial covering XADC_tb but none of them are using VHDL. I've tried to do it for my own but everything what i"ve tried failed. Could you please tell me how am i suppose to simulate analog signal? Or help me write testbench for that? My code of components etc.: entity top_main is Port ( CLK : IN STD_LOGIC; -------------------------------- ADC_6N_K3 : IN STD_LOGIC; -- vauxn6 ADC_6P_J3 : IN STD_LOGIC; -- vauxp6 -------------------------------- ADC_7N_M1 : IN STD_LOGIC; -- vauxn7 ADC_7P_M2 : IN STD_LOGIC; -- vauxp7 -------------------------------- ADC_14N_M3 : IN STD_LOGIC; -- vauxn14 ADC_14P_L3 : IN STD_LOGIC; -- vauxp14 -------------------------------- ADC_15N_N1 : IN STD_LOGIC; -- vauxn15 ADC_15P_N2 : IN STD_LOGIC; -- vauxp154 -------------------------------- UART_TXD_pin : IN STD_LOGIC; -- INPUT '1' UART_RXD_pin : OUT STD_LOGIC -- UART OUT TO COMPUTER ); end top_main; type pmod_addresses is array (0 to 3) of std_logic_vector(6 downto 0); constant adress_pmod : pmod_addresses :=("0010110","0010111","0011110","0011111"); -- 6/7/14/15 -> PORTS XADC -- signal DataValid : STD_LOGIC; -- DATA IN VALID signal DataReady : STD_LOGIC; -- DATA READY (FOR FFT) signal index : INTEGER := 0; -- INDEX FOR ADC signal DataOut : STD_LOGIC_VECTOR(15 DOWNTO 0); -- DATA ADC OUT signal nr_adc : STD_LOGIC_VECTOR(6 downto 0) := adress_pmod(0); COMPONENT XADC_block_input PORT ( di_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0); daddr_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0); den_in : IN STD_LOGIC; dwe_in : IN STD_LOGIC; drdy_out : OUT STD_LOGIC; do_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); dclk_in : IN STD_LOGIC; vp_in : IN STD_LOGIC; vn_in : IN STD_LOGIC; reset_in : IN STD_LOGIC; ------------------------------------ vauxp6 : IN STD_LOGIC; vauxn6 : IN STD_LOGIC; vauxp7 : IN STD_LOGIC; vauxn7 : IN STD_LOGIC; vauxp14 : IN STD_LOGIC; vauxn14 : IN STD_LOGIC; vauxp15 : IN STD_LOGIC; vauxn15 : IN STD_LOGIC; ------------------------------------ channel_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); eoc_out : OUT STD_LOGIC; alarm_out : OUT STD_LOGIC; eos_out : OUT STD_LOGIC; busy_out : OUT STD_LOGIC ); END COMPONENT; XADC_PORT_MAP: XADC_block_input PORT MAP ( di_in => X"0000", daddr_in => nr_adc, den_in => DataValid, dwe_in => '0', drdy_out => DataReady, do_out => DataOut, dclk_in => CLK_128MHz, vp_in => '0', vn_in => '0', reset_in => MASTER_RESET, ------------------------------------ vauxp6 => ADC_6P_J3, vauxn6 => ADC_6N_K3, vauxp7 => ADC_7P_M2, vauxn7 => ADC_7N_M1, vauxp14 => ADC_14P_L3, vauxn14 => ADC_14N_M3, vauxp15 => ADC_15P_N2, vauxn15 => ADC_15N_N1, ------------------------------------ channel_out => open, eoc_out => DataValid, alarm_out => open, eos_out => open, busy_out => open ); -- ADC DATA FORWARDING -- p_XADC_PORT_ADDRESING: process(CLK_128MHz) begin if(rising_edge(CLK_128MHz)) then if(DataReady = '1') then case nr_adc is when adress_pmod(0) => XADC_1_FIR_1 <= DataOut ; when adress_pmod(1) => XADC_2_FIR_2 <= DataOut ; when adress_pmod(2) => XADC_3_FIR_3 <= DataOut ; when adress_pmod(3) => XADC_4_FIR_4 <= DataOut ; when others => XADC_1_FIR_1 <= (others=>'0'); XADC_2_FIR_2 <= (others=>'0'); XADC_3_FIR_3 <= (others=>'0'); XADC_4_FIR_4 <= (others=>'0'); end case; if index = 0 then index <= 1; else index <= 0; end if; nr_adc <= adress_pmod(index); end if; end if; end process p_XADC_PORT_ADDRESING; Here's generated TESTBENCH CODE: library IEEE; use IEEE.Std_logic_1164.all; use IEEE.Numeric_Std.all; entity top_main_tb is end; architecture bench of top_main_tb is component top_main Port ( CLK : IN STD_LOGIC; ADC_6N_K3 : IN STD_LOGIC; ADC_6P_J3 : IN STD_LOGIC; ADC_7N_M1 : IN STD_LOGIC; ADC_7P_M2 : IN STD_LOGIC; ADC_14N_M3 : IN STD_LOGIC; ADC_14P_L3 : IN STD_LOGIC; ADC_15N_N1 : IN STD_LOGIC; ADC_15P_N2 : IN STD_LOGIC; UART_TXD_pin : IN STD_LOGIC; UART_RXD_pin : OUT STD_LOGIC ); end component; signal CLK: STD_LOGIC; signal ADC_6N_K3: STD_LOGIC; signal ADC_6P_J3: STD_LOGIC; signal ADC_7N_M1: STD_LOGIC; signal ADC_7P_M2: STD_LOGIC; signal ADC_14N_M3: STD_LOGIC; signal ADC_14P_L3: STD_LOGIC; signal ADC_15N_N1: STD_LOGIC; signal ADC_15P_N2: STD_LOGIC; signal UART_TXD_pin: STD_LOGIC; signal UART_RXD_pin: STD_LOGIC ; constant clock_period: time := 10 ns; signal stop_the_clock: boolean; begin uut: top_main port map ( CLK => CLK, ADC_6N_K3 => ADC_6N_K3, ADC_6P_J3 => ADC_6P_J3, ADC_7N_M1 => ADC_7N_M1, ADC_7P_M2 => ADC_7P_M2, ADC_14N_M3 => ADC_14N_M3, ADC_14P_L3 => ADC_14P_L3, ADC_15N_N1 => ADC_15N_N1, ADC_15P_N2 => ADC_15P_N2, UART_TXD_pin => UART_TXD_pin, UART_RXD_pin => UART_RXD_pin ); stimulus: process begin -- Put initialisation code here -- Put test bench stimulus code here stop_the_clock <= true; wait; end process; clocking: process begin while not stop_the_clock loop CLK <= '0', '1' after clock_period / 2; wait for clock_period; end loop; wait; end process; end; Also i've set all the important settings in XADC IP CORE: Best Regards, Michael
  5. dear @jpeyron I've change the type of ram to "Simple Dual Port RAM". Here is the entity for this ip core: entity fft_mem_1024_32bit is Port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); clkb : in STD_LOGIC; enb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); I think using this is better than single port. Could you please tell me how do i change the enb status once the memory is full(32 bits x 1024 elements)? Best Regards, Michael
  6. Hello! I've created memory block using ip catalog that keep the data received from FFT in vivado, and now i want to access the data. I know that i need to increase the address but I'm not sure exactly how i am suppose to do it. Could you please recommend me something? Here's my code memory block with address incrementation: COMPONENT fft_mem_1024_32bit PORT ( clka : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; Memory_fft_mem32_1: fft_mem_1024_32bit PORT MAP ( clka => dclk_in, ena => '1', wea => FFT_MEM_VALID_1, addra => adres_RAM_1, dina => FFT_MEM_1, douta => MEM_DATA_OUT_1 ); Adresowanie_Pamieci_1: process(dclk_in) begin if(dclk_in'event and dclk_in = '1') then if(FFT_MEM_VALID_1 = "1") then adres_RAM_1 <= std_logic_vector(unsigned(adres_RAM_1) + 1); if (adres_RAM_1 > X"3FF") then adres_RAM_1 <= "0000000000"; end if; end if; end if; end process;
  7. @D@n That's correct. But since the data comming out of XADC is std_logic_vector(15 downto 0), how do i seperate img part from bits? You are able to seperate the imaginary parts after FFT not before, and still the question is how to implement it into VHDL. Michael
  8. @D@n Is it better to create 8x fft or 1 fft with 8 channels? Also to create inverted FFT (like @xc6lx45 said - conjugated fft) - you've got to invert the imaginary part of the output. How do i invert imaginary part of the (fft) output vector and leave the rest ?
  9. dear @jpeyron May i ask about 5 things connected to fft and to signal processing? - "Number of Channels" - what is it used for? I've gone through "FFT v9.0" from xilinx but the only information about that is that can be selected is from 1 to 12. - "Transform Length" - is it the lenght of the input data to FFT core? is there any rule like sampling rate must be 2x max. freq.? - "Target Clock Frequency" - Can i go for 450MHz if my board (basys3) has Internal clock speeds exceeding 450MHz? What are the limits. It's good to know (i think) that The Basys3 board includes a single 100MHz oscillator connected to pin W5 - "Target Data Throughput" - How to know what Throughput should be set? Edit: To create ifft using vivado you've got to change the sign of imaginary part and then proceed with fft.
  10. @jpeyron I think this might help! Since XADC in Basys3 works sequentially (i've chosen it to works this way) and it goes from 1 to 8 then i can increase memory addres by 1 after the last (xadc) adress check, and restart the value when it gets up to 4096. Here's goes nothing: -- in the architecture -- signal adres_RAM : integer := 0; OutputBuffer: process(dclk_in) begin if(dclk_in'event and dclk_in = '1') then if(DataReady = '1') then case nr_adc is when adres_pmod(0) => dina_1 <= DataOut; when adres_pmod(1) => dina_2 <= DataOut; when adres_pmod(2) => dina_3 <= DataOut; when adres_pmod(3) => dina_4 <= DataOut; when adres_pmod(4) => dina_5 <= DataOut; when adres_pmod(5) => dina_6 <= DataOut; when adres_pmod(6) => dina_7 <= DataOut; when adres_pmod(7) => dina_8 <= DataOut; adres_RAM <= adres_RAM +1; when others => dina_1 <= "0000000000000000"; dina_2 <= "0000000000000000"; dina_3 <= "0000000000000000"; dina_4 <= "0000000000000000"; dina_5 <= "0000000000000000"; dina_6 <= "0000000000000000"; dina_7 <= "0000000000000000"; dina_8 <= "0000000000000000"; end case; if indeks = 0 then indeks <= 1; else indeks <= 0; end if; if adres_RAM = 4096 then adres_RAM <= 0; end if; nr_adc <= adres_pmod(indeks); end if; end if; end process; end Behavioral;
  11. @D@n RS-232 connection to the PC *
  12. @xc6lx45 about signal processing - if you multiply fft of one signal and multiply it with inversed fft of second one - the answer is the peak from xcor. In my case its the location of microphones. I need to implement FFT / iFFT - multiply both and proceed the output data with RS to my PC.
  13. Unfortunately i need to use FFT inside of an FPGA. I need to save data received from 2 XADC ports - use FFT on one and iFFT on the second one and multiply each other. Then proceed the data via RS to PC.
  14. Hello, A while ago i've managed to receive data from XADC using my board Basys3 and now i need to use FFT, iFFT and proceed the output from these to via RS to my computer. Could you please show me examples of FFT / iFFT and RS connection? I've been trying to find something online, but there is nothing as simple as that. Best Regards, Michael
  15. Hello, @jpeyron I've read all of the examples in links that you've included and the most important one is the second one. However there is no line that increment the address value. How does it work? Does it increase the address with every rising edge or maybe it fulfill the whole 256 array with data? The code is from link. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ram_example is port (Clk : in std_logic; address : in integer; we : in std_logic; data_i : in std_logic_vector(7 downto 0); data_o : out std_logic_vector(7 downto 0) ); end ram_example; architecture Behavioral of ram_example is --Declaration of type and signal of a 256 element RAM --with each element being 8 bit wide. type ram_t is array (0 to 255) of std_logic_vector(7 downto 0); signal ram : ram_t := (others => (others => '0')); begin --process for read and write operation. PROCESS(Clk) BEGIN if(rising_edge(Clk)) then if(we='1') then ram(address) <= data_i; end if; data_o <= ram(address); end if; END PROCESS; end Behavioral;
  16. Hello! I've been trying to work with A/D converters and after a while i've finally understood how do they work. Now want to proceed my data to memory blocks. As far as i know i need to increment the given adress to be able to fulfill the whole memory cell. Could you please tell me how am i suppose to do it? Here's my code.. Best Regards, Michael
  17. Hi @jpeyron Thanks a lot for your answer, today im going to look into this! Best Regards, Michael
  18. Hello, Could you please explain to me how to operate xadc ports on my basys3 board using VHDL? Reference is in verilog and it's not really that helpful. I'm trying to create cross-correlation out of microphone signal but i dont know how to use xadc. Best Regards, Michael
  19. I didn't restart the value of clk_vector - so after reaching 100000000 it continued up to integer value which is 2^32...
  20. I've created this simple mod16 counter using basys3 board and something is not right with my clock. The code itself do works, however one count (changing from "1" to "2" etc.) last 40 seconds, instead of 1 second! I've tried to lower the "clk_vector" if condition to 1 but it didn't help either. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity mod_16_k is Port ( sw : in STD_LOGIC_VECTOR (3 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; led : out STD_LOGIC_VECTOR (15 downto 0)); end mod_16_k; architecture Behavioral of mod_16_k is signal clk_vector :integer; signal clk_vec2 :std_logic_vector(15 downto 0); begin zegar_wew : process(clk) begin if(clk'event and clk = '1') then clk_vector <= clk_vector + 1; if(clk_vector = 100000000) then clk_vec2 <= std_logic_vector(unsigned(clk_vec2) + 1); end if; end if; end process; led <= clk_vec2; end Behavioral; The .XDC lines for clock are: set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] If we check the basys3 datasheet, the clock is connected to "W5" port.: Do you have any idea, what might be the problem in here? It might be connected with detecting the rising edge of an clk, however all of the changes (from 1 to 2 etc.) last ~40 seconds.
  21. @D@n well i've got a lot to learn first. Thanks for advices
  22. Hello, I've been trying to find few informations about BASYS3's xadc ports. By any chance do you know: - what's the sampling rate (i think its 1 Mpsp)? - what's the delay between ports? - is it compatible with microphone output (diff or single ended)?
  23. @D@n I'm begginer with vhdl and trying to create simple projects. Doing it in C it's easy but with fpga something is wrong. I want to check the button state - get the vectors value and add up both of them. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; entity calc is Port ( switch : in STD_LOGIC_VECTOR (7 downto 0); button : in STD_LOGIC_VECTOR (2 downto 0); vec1,vec2 : inout STD_LOGIC_VECTOR (7 downto 0):= "00000000"; sum : inout STD_LOGIC_VECTOR (7 downto 0); led : out STD_LOGIC_VECTOR (7 downto 0) ); end calc; architecture Behavioral of calc is begin led <= switch; process (button,switch,vec1,vec2,sum) begin if (button(1) = '1') then vec1 <= switch; elsif (button(2) = '1') then vec2 <= switch; elsif (button(0) = '1') then sum <= vec1 + vec2; led <= sum; end if; end process; end Behavioral;
  24. Hello! I'm new in here. I've wanted to create boolean calculator with basys3 board and mine idea is: - use switches to created 8 bits std_logic_vector. - use leds to represent vector value. - use one of the buttons to remember the bits value. - create another vector with switches and use leds to show it once again. - use button to create another variable to remember the bits value. - use second button to represent the boolean result of adding both of the vectors. While using switchs and leds is not a big deal - creating variables with push buttons is kinda hard task. Could you please explain to me, how to create those? Best regards, Michael