AndrewHolzer

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AndrewHolzer last won the day on February 1

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About AndrewHolzer

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  1. artix nexys 4 and keyboard

    Hello @nisarg_shah114, The Nexys 4 has an onboard USB host connector with a microcontroller that sits between it and the FPGA. The microcontroller will handle the USB HID protocol and emultates PS/2 bus signals. There will be no need for an external PS/2 to USB converter at all. This section of the Nexys 4 reference manual has details regarding the keyboard connection. The section before it gives details to the HID controller. I hope this information helps you. Do not hesitate to ask any questions you may have, and I will do what I can to help. AndrewHolzer
  2. Accessing PS MIO (LED and 2 push buttons)?

    Hi @dand400, Glad to hear that you've fixed your issue and reported it here! Best regards, AndrewHolzer
  3. Project using PS alone on zynq

    Hi @Tech_Enthusiast_007, All you really need is the Zynq Processing System IP core and you'll be on your way. Add the IP core to your design and hit Run Block Automation. This will initialize the block and setup the Ethernet and UART peripherals for you to use. Once that step is completed, you can route the output from FLCK_CLK0 to M_AXI_GP0_ACLK and then hit Validate Design. The tools should tell you that everything is good to go. Create the wrapper, generate bitstream, then export the design to SDK. Once you're in SDK, you can create your project, but base it off the Hello World template to test the UART. You can then start coding your project from there. The Zynq block is just a block representation of the processing half of the Zynq chip, and is required for you to export the hardware description to SDK. I hope that this has proven to be helpful to you! Let me know if you have any further questions and I will be happy to assist you, AndrewHolzer
  4. basic AXI_timer cannot interrupt successfully

    @Cynthia, I am glad to hear that you were able to find what was giving you troubles and want to thank you for posting your solution. Good luck with the rest of your project! Regards, AndrewHolzer
  5. basic AXI_timer cannot interrupt successfully

    @Cynthia, I've run through the guide that you linked with the standalone OS. I was able to get everything working with the interrupts from the custom IP core being triggered. Some of the code has depricated, like the Xuint32 data types, but if you follow the warnings that SDK gives you you'll figure it out. You can run the code and see output indicating how many times the interrupt routine has executed. I found that main won't complete execution and never reaches the "Waiting for Interrupts...\n\r" bit. I was able to comment out the xil_printf method in handler() and main was able to complete. Both of these examples demonstrate that the interrupt from the custom IP core is being captured. Let me know if you have any issues trying this out, AndrewHolzer
  6. basic AXI_timer cannot interrupt successfully

    @Cynthia, Once again I want to thank you for your patience. I want to update here so you aren't left wondering what I've been up to. I have been able to replicate your exact issue where the code executes twice and the interrupt for the timer does not trigger. I've been able to get the peripheral test to succeed on the timer interrupt and exit main, but this was done with a bsp that was made using the standalone OS type. This was done with no changes made to the peripheral test code underneath either the standalone or xilkernal OS type. This leads me to believe that this is an issue with the xilkernal itself. I haven't quite tracked down the issue yet but I am digging further. I believe I am on the right track here though, and will be reading up on the xilkernal to see if I can find out what the issue is. If the application you have in mind doesn't require the xilkernal OS type, I suggest that you try the standalone OS type and see if that suits your needs. Since you are specifically generating the bsp with the xilkernal type, however, I assume it is necessary in someway. I'll keep up my work here and update when I've found something. In the meantime take care, AndrewHolzer
  7. basic AXI_timer cannot interrupt successfully

    Hi @Cynthia, I want to thank you for your patience. I've been trying to recreate the results you are seeing but have been unable to do so. Can you send me an image of the block diagram of your design? How are you programming the Nexys Video FPGA? What version of Vivado and Vivado SDK are you using? One solution that was recommended to me was to go into your project directory and either delete the *.sdk directory or rename it to something else. Once you have done that, go back into Vivado and export design once more and then launch sdk. Go through the process of creating the Peripheral Test application in SDK and launch it. You want to do this because there can be issues when you update the FPGA design in Vivado and then go back to SDK with those revisions. That could be the reason as to why you are seeing this new issue. Let me know how that goes, and the information I've asked for if this still does not work. Best of luck, AndrewHolzer
  8. basic AXI_timer cannot interrupt successfully

    @Cynthia, I've noticed that you haven't included a MIG in your block design. I suggest that you follow the Getting Started with Microblaze guide for the Nexys Video for help in setting up a base design. I don't have a Nexys Video on hand myself, but I did run through the same process using my Arty. In my first design iteration, I didn't include a MIG and my design failed as yours did. In my next pass through on the design, I dropped in a MIG and regenerated my BSP sources. I ran the test once more and the interrupt test for the timer passed. There will be a pause of a few seconds when testing the axi_timer, so some patience is required. Let me know if this fixes your issue, and if not I will work with you to find a solution, AndrewHolzer
  9. No Ouput PMOD CLS

    @artvvb and @jasonbla20, I was also thinking it may be that the IP core is configured with the new UART pin connection, whereas the PmodCLS follows the old convention. I don't see how the IP core would be pushed to release if that wasn't accounted for and have been working on verifying that the IP core accounts for that discrepancy. If you can verify yourself, then go right ahead. It probably isn't the case, but is something that should be kept in mind when troubleshooting this case. AndrewHolzer
  10. PMOD connector spacing

    Hi @Solomon Kalbore, I answered a similar question here. In short, the center-to-center distance between two PMOD headers is 0.9", so the center-to-center from pin1 on one header to the next should be the same as well. The comment includes a link to the PMOD standard, which has other bits of info should you need it. Regards, AndrewHolzer
  11. Image Capture System

    Hi @jem2k, I was able to locate the project buried within our server archives. I've included the project zip here for you and anybody else who may be interested in this project in the future. I've also found another project that targets the Nexys2 that does edge detection. I'm going to include it as well as an extra goodie. Good luck with your project! AndrewHolzer 23 Image Capture Watermark - Ceapa.zip 14_Image_Processing_with_Edge_Detection_-_Gidro.zip
  12. Image Capture System

    Hi @jem2k, I've tried to do some digging to find alternative sources for the project you are asking about. I haven't found anything, so instead I have asked if it possible that the project still exists somewhere on our site. I will return to you when I have an answer. Thank you for your patience, AndrewHolzer
  13. Arty and I2C to query PmodTMP2

    Hello Clipper, The pmod_bridge doesn't configure the I2C ports to have pull-ups. I don't know about the axi_iic block, but because the pmod_bridge sits between it and the output port I don't believe that the axi_iic block would configure the output ports to have pull-ups either. This is the first thing that I suspect is giving you troubles. You can Open Implemented Desgin and from there open the Window>I/O Ports page, where you can configure the pull type that you would like the pin to have. Let me know if this fixes the issues that you are seeing here and if they are not then I will work with you until there are no further issues. Looking forward to hearing back! AndrewHolzer
  14. Unable to load Vivado License Manager

    Hello @B Sully, A quick Google search turned up this Xilinx support case and solutions that you can pursue to correct this issue. What version of Vivado are you trying to install? AndrewHolzer
  15. Power Supply for myProto Protoboard for NI myRio

    Hi @Cameron, That symbol indicates you need a center positive DC Barrel Jack with a supply that can deliver up to 17VDC. The jack itself is seen at the end of this wall-wart. There isn't an included power supply in the myProto package, so you will have to purchase one if you do not already have one. The supply I linked will work for this. AndrewHolzer