Commanderfranz reacted to sLowe in adc embeded in board
All of our Artix-7 and Zynq boards have this capability through the xadc embedded on the FPGA. Here is a link to the XADC datasheet. http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
If this satisfies your requirements, one of the xadc reference projects located on our wiki would be a good place to start.
This is for the basys 3 https://reference.digilentinc.com/basys3:xadcdemo
Commanderfranz reacted to JColvin in analog discovery in Europe with academic discount
You can get the Analog Discovery (among other products) with the academic discount through one of our European distributors (Trenz). From my understanding you would still need to pay the import tax, but the shipping price will be reduced. Looking at their site, it seems that the listed price includes these sorts of things already.
Let me know if you have any more questions.
Commanderfranz reacted to JColvin in MRK+ Line Kit
To my surprise, at this point in time there is not a way to order with the bracket with the lip. I'll ask to see if this angled bracket can be sold individually in the future. In the meantime, I would recommend either bending the metal yourself from the part you found (it's fairly soft for metal, so you can bend it with a good pair of pliers) or if you have access to a 3D printer, downloading and printing out the angled part here.
Sorry that I can't be of more help.
Commanderfranz reacted to Bianca in Vivado design Software limitation arty board
Yes indeed, device limited means that you could use it only with the FPGA that Arty is equipped with. In this case xc7a35ticsg324-1L.
If you want to use Vivado with other boards or FPGA you can always install the WEBPACK Edition. This one is free and comes with almost the same features as the Design Edition.
Commanderfranz reacted to JColvin in Nexys 4 board
If I'm understanding your question correctly, you want to know what pins you need for the second seven segment display to get it running. The way the Nexys 4 is set up, both seven segment displays share the same cathodes (each little portion of the digits), but all have separate anodes. Looking at the XDC file for the Nexys 4 (available in the Nexys 4 Resource Center), one seven segment display uses the anode names AN0 through AN3, while the other display uses AN4 through AN7. In principle then, when you update the seven segment display you have running now, you would tell the other display to also update its digits (with its set of anodes) simultaneously.
Let me know it this answers your question!
Commanderfranz reacted to Bianca in Worksheet Solutions
If you are asking for the solution from the exercise on Real Analog, you can find the solutions here . If you are looking for homework solution, we don't have them. On that page you can find the whole documentation. I hope it helps.
Commanderfranz reacted to TommyK in XADC output for module instantiation
I think you'll want to make a small state machine to accomplish this.
reg [2:0] state=0'b000;
[email protected](posedge(clk)) begin
case 0: begin
case 1: begin
(and so forth)
Commanderfranz reacted to sLowe in MUX 2x1 using VHDL
On top of this module I would use the clocking ip wizard to generate these two frequencies. Once you do this, you can feed the two clocks into your mux. However, you may get some critical warnings about logic on clocks but since you are using them for PWM and not actual clocking, this should not affect your design.
Hope this helps a bit!
Commanderfranz reacted to Sergiu in Getting Started with Vivado guide
You can find reference projects and tutorials on several channels. The first one you should check out is our wiki:
I believe the tutorial you are referring to is this one: https://reference.digilentinc.com/basys3:gsg
Although it is centered on the Basys3 board, it can also be applied to Arty since they both carry the same FPGA.
Commanderfranz reacted to Bianca in cannot stop synthesis run Advanced I/O Demo on Nexys 4 DDR
The problem is a Vivado bug. You are using a different version of Vivado that the one used for creating the project. The version used is 2015.1. If you use this you won't have errors. In order to see the Demo working on newer Vivado version, you should upgrate your IP core. It says in your warnings to " select 'Report IP Status' from the 'Tools/Report' ". Vivado 2015.2 or 2015.3 might give you some errors, so I suggest using the last version of Vivado 2015.4
Get your IP up to date then reopen your project and run a synthesis.
Commanderfranz reacted to AndrewHolzer in ARTY - Is encryption supported on Arty boards?
Thank you for pointing out that encryption isn't just a matter of SW tools. I have some answers for your question, which I am happy to get into further if I don't give you a clear enough answer here.
For your first question, currently the on-board USB-JTAG solution doesn't support eFUSE configuration due to how the toolchain confirms the cable speed. This should change in Xilinx's 2016 release of Vivado.
For your second question, the J8 connection hasn't been tested with a Xilinx USB Platform Cable II, but has been tested with plenty of other cables. You should be able to use the Platform cable to configure the eFUSE registers through the header.
Please let me know if I can further clarify anything for you,
Commanderfranz reacted to AndrewHolzer in ARTY - Is encryption supported on Arty boards?
I did some digging through various Xilinx documents to find you an answer and I found that eFUSE encryption is supported on the Arty boards in Vivado 2014.4 onwards, from this page. ISE can configure a limited subset of 7 series devices via iMPACT, however the Arty isn't one of these devices.
As far as configuring the eFUSE registers, it is beyond what we do here at Digilent. You're treading in open waters from here. I suggest that you look through the Vivado User Guides to understand how to use the tools for eFUSE configuration.
Hope this helps you,
Commanderfranz got a reaction from AbdulSattar Qaisrani in Using Adept with the Spartan-3E
Let me just start by saying, I'm sorry you've had such trouble getting your spartan 3E board working.
I wanted to post to clear up one point of confusion. Nate suggested
He didn't suggest that you buy the JTAG programming cable but suggested that you use iMPACT to program the board. I can understand your confusion based on the wording of his suggestion, so let me clear it up for you. All Digilent boards contain a JTAG programming circuit natively so they do not need JTAG cables, as is indicated on the product pages for the JTAG cables. iMPACT is the correct software to program the board, so as long as you are using iMPACT, you should be able to connect to the board.
When I searched around for this problem I found the USB cable installation guide from Xilinx. You can follow the directions here to reinstall cable drivers, since you and Nate have figured out it is a cable driver issue. I would also highly suggest that you download the latest version of ISE. It's possible that this is an issue with the version you are using, that was subsequently fixed.
Commanderfranz reacted to cristian.ignat in Nexys Video HDMI How To?
You can find the example on the following link: https://reference.digilentinc.com/nexys-video:hdmi
To run this example, you should have vivado 2015.3. You can find the HDMI project on ".../NexysVideo-master/Project/hmdi" path. If you are following all the steps, this should run without errors. Your error is strange because in our xdc file, we don't have the TMDSn signal defined.
Commanderfranz reacted to JColvin in Virtex5 & vmod cam
Hi Anand Immanuel,
I don't believe we have anything for the VmodCAM that works with a Virtex5. All the demos we have available for the VmodCAM are for the Atlys (a Spartan 6), so you should be able to get some information on how to interface with the VmodCAM from there. The VmodCAM is a retired product so there is limited support that we can offer.
Commanderfranz reacted to Cristian.Fatu in Create Nexys4 .mcs file in Vivado
Please open http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf and go to page 13, chapter Programming Configuration Memory Devices.
First of all, you might not need to generate the mcs file, as you can program the QSPI with the bin file, generated when the bit file was generated. For this, you just have to add the Configuration Memory device (explained in the above mentioned document, enter S25FL128 and select the first from the list). Then, program it with the bin file.
If you still want to build the mcs file, here is how you can do it:
I have used the Nexys4 Basic User Demo, available here: https://reference.digilentinc.com/nexys:nexys4:gpiodemo
After generating the Bitstream, I have used the following commands in the TCL script window:
- cd <project location> lab1.runs\impl_1 (location where the bit is)
- write_cfgmem -format mcs -interface SPIx1 -size 32 -loadbit "up 0x0 Nexys4UserDemo.bit" -file Nexys4UserDemo.mcs
Then, the mcs file is created. In order to program, add the Configuration Memory device as explained above, and then program the memory with the mcs file.
In the end, please do not forget to power off and back on the board, having MODE switch on QSPI.
Commanderfranz reacted to JColvin in PMOD in Zedboard.
So this is out of the scope of what Digilent does, but here is what I found. Around the 3:06 minute mark in the fourth video, you will see that when they pick the AXI4LITE interface from the dropdown menu for "Target Platform Interfaces" you will notice at the bottom of the dropdown list there are the various Pmod ports listed which you can select.
So for your project, what you would need to do is create your own custom 'block' within Simulink that performs whatever process you want on an input and then sends the result to an output. Once you have your block, you will be able to choose different Pmod ports for your input and output (or 'inport' and 'outport' as they listed).
Unfortunately, that is as far as my understanding of what you would need to do goes.
Commanderfranz reacted to Bianca in Zybo base system design
Well first of all, the processor has the data bus HP0 and it uses it to read/write from DDR. VDMA is used to automatically display on the monitor, so the VDMA is connected to HP0 bus in order to r/w in DDR and the user needs to control the VDMA to access the memory. The AXI interface is used for the communication between the processor and the FPGA. You need it to control from the processor the modules utilized in the FPGA.
Regarding the clocking, the 100MHz clock is created as standard for the ip cores we create to use in the project. In general the cores works on 100MHz. The 150MHz frequency is needed for the display. The HDMI needs a frequency of 148MHz and the data reading from DDR needs to be faster than the pixel frequency for 1080p resolution which is used for HDMI in this project.
The design, I suppose, was build for Vivado 2013.4
Commanderfranz got a reaction from JColvin in Basys 3 Xilinx Vivado Design Suite Voucher
These are all very common and great questions about licensing.
The Voucher that you can buy with the Basys 3 is for the Design Edition of Vivado. Just as in ISE you can get the free webpack version license for vivado, which will allow you to generate a bitstream.
You can view the differences between the Design Edition and Webpack edition on this graph.
The Voucher that you can buy with the Basys 3 allows you to upgrade to the latest versions for a year, and then remains static.
The Voucher that comes with the Basys 3 is node locked, as is the webpack edition. This means that you can only use it on one computer.
Hope this helps!
Commanderfranz got a reaction from JColvin in cmod 6 clock
To access the clock for basic VHDL or Verilog designs you have to uncomment the clock line in your UCF file.
That is, this line:
NET "CLK" LOC = "N8" | IOSTANDARD = LVCMOS33;
Then you use "CLK" to connect it in your design.
You can find the master UCF file at reference.digilentinc.com/cmod_s6:cmod_s6