Commanderfranz

Technical Forum Moderator
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  1. Like
    Commanderfranz reacted to BKallaher in basys 3 ila performance   
    Hi andrei,
    These are the results I am able to get on the Basys 3. The ILA is set up with 64 probe ports and a data depth of 1024.
    LUTs - 2694 of 20800 LUTRAM - 476 of 9600 Flip-Flops - 4126 of 41600 Block RAM - 6 of 50 Overall just under 20% of the FPGA fabric is used by the ILA.
    Thanks,
    BKallaher
  2. Like
    Commanderfranz got a reaction from hamster in Invalid I/O Standard 'TMDS' when using Nexys Video .xdc file   
    Hi nversluis,
    Thanks for letting us know about that, and sorry for the confusion that it caused. 
    We have sent a note off to our applications team to get that fixed. 
    Kaitlyn
  3. Like
    Commanderfranz reacted to Billel in Genesys 2 current measurement problem   
    Hi again
    I have solved the problem by initialise the I2C peripheral and ensure that I have correctly map the peripheral in the bloc design.
    Thank you Mr Dan for your help.
  4. Like
    Commanderfranz reacted to Gra in Is the Spartan 3AN700 FPGA the same as the Spartan-3E Starter Board?   
    Hi Zwarren,
    The Spartan 3A and Spartan 3AN development board have the same peripherals. The 3A was more common than the 3AN, so probably easier to find one of those.   Having said that, here is a 3AN on ebay   http://www.ebay.com/itm/Xilinx-Spartan-3AN-Non-volatile-Secure-FPGA-Development-Board-Starter-/262340836625?hash=item3d14bb7d11:g:u2gAAOSwr7ZW65bP   Gra  
  5. Like
    Commanderfranz reacted to AlistairCheeseman in Nexys4 Ethernet Example   
    Just to say thanks the example located at
    https://reference.digilentinc.com/nexys:nexys4:gsmbs
     
    works perfectly, after getting it working with little effort what so ever I am now going to delve into the code and get it working for what i need it for.
    Thanks for all the quick responses!
  6. Like
    Commanderfranz reacted to jpeyron in Nexys 3 Can't add Digilent Shared Memory Bus from BSP 2.8   
    Hi Jonas,
    Sorry for the late response. When I opened a Base System Builder project it started with the Digilent Shared Memory Bus. I would suggest to manually install the ipxact at
     "<Xilinx_Install_Dir>\<EDK_Version>\ISE_DS\EDK\data\wizards\" described in the readme test
    in Nexys3_BSB_Support_v_2_8\Digilent_AXI_IPCore_Support_v_1_35.
    I also followed the Nexys3_AXI_BSB_Support pdf in the Nexys3_BSB_Support_v_2_8\Nexys3_AXI_BSB_Support folder.
     
    Hopefully this resolves the issue!
    thank you,
    Jon




  7. Like
    Commanderfranz reacted to hamster in Invalid I/O Standard 'TMDS' when using Nexys Video .xdc file   
    You want to use TMDS_33 - for example:
    set_property -dict { PACKAGE_PIN Y1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[0] }]; 
    set_property -dict { PACKAGE_PIN W1    IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[0] }]; 
    set_property -dict { PACKAGE_PIN AB1   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[1] }]; 
    set_property -dict { PACKAGE_PIN AA1   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[1] }]; 
    set_property -dict { PACKAGE_PIN AB2   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_n[2] }]; 
    set_property -dict { PACKAGE_PIN AB3   IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_p[2] }]; 
    (this is from an Artix 7 project for the Nexys Video, so you will have different pin locations - but you get the gist - it is TMDS_33)
  8. Like
    Commanderfranz reacted to jpeyron in Board files for the Zedboard   
    Hello,
    The board file for the Zedboard is automatically shipped with Vivado. That is why it isn't in the board files at https://reference.digilentinc.com/vivado/boardfiles. 
    thank you,
    Jon

  9. Like
    Commanderfranz reacted to [email protected] in FPGA interconnection with RFID   
    Did you forget the Chip Select line as part of your master controller.  It's a required part of the SPI protocol for framing purposes.
    Dan
  10. Like
    Commanderfranz reacted to [email protected] in How to interface video camera to Nexys 4 DDR   
    Looking at the USB port on he Nexys4 DDR, it looks like it's a slave port to the computer that is hosting the board rather than an open port which may be used by something else.  Often, Digilent connects this USB port to a small microcontroller on the board rendering it really useful for the one purpose, but not very reprogrammable.
    As for PMod's, I'll let the Digilent staff prove me wrong, but I don't think any of the PMod's will work with a camera.  Camera's tend to want to support high speed data streaming, and you sort of need to plan for that from the beginning.
    Speaking of planning from the beginning, have you considered the Nexys Video?  That board has inputs for both DisplayPort and HDMI graphical inputs, as well as an HDMI ouput.  It shouldn't be too hard to find a camera that outputs one of these formats and HDMI displays are becoming more commonplace ...
    Dan
  11. Like
    Commanderfranz reacted to [email protected] in How to read/write to p30 parallel flash memory on digilent genesys   
    1st, I'm not Digilent.
    2nd, I'm not sure I could debug your code from here.  Sorry.
    Do you have the specification sheet for the strataflash?  I managed to get one for the device I was working with a while back by googling the part number.
    3rd, I don't own a strataflash.  I was going to purchase the 3E development board at one time, and built all the RTL I thought I would need to support it, but given that I didn't buy the board, I don't know if any of the RTL I built would've truly worked.  I did manage to write a thorough testbench for the flash and Verilog to control the testbench, so I'm pretty confident that I was close to getting it to work.
    4th, the approach I'm about to share did work for me on SPI flash--which I have gotten to work.
    So, with all of the above caveats aside ...
    Here's what has been successful for me: 1) I often write a simulator for the flash as my first step.  Some people call this a test-bench, although since I've been using Verilator as my build language, my "simulator"/testbenches are all built in C++ and they are fully functional. (I can even load my simulated flash with whatever I want initially, so that I can know the read works before the write.)  Building this required the specification sheet for the flash, and walking through that spec sheet over and over.  2) I then work my Verilog code against the simulator until it works.
    For example, as I recall, the strataflash I was looking at had several different read modes and you had to carefully control and select which mode the device was in.  You could read various things from the device including status registers, ID fields, all in addition to the actual memory of the device.  By using my "simulator", I always knew what mode the flash was in versus what mode I wanted it to be in.  I could then guarantee all the transitions happened when I needed them to and so on.  For example, can you read the status register from the strataflash?  It might tell you what you are doing wrong.
    Writing to a flash is much more complicated than writing to a memory.  You do know that you need to erase the flash first before you can write to it?  Erasing turns all the bits to '1's, writes selectively turn '1's to '0's.  Erases only work on blocks, so on and so forth.  It's really quite complicated.  You should become very familiar with the specification. 
    I guess what I'm saying is, your code above looks a bit too simplistic.  Take a good long hard at the specification sheet.  Work your simulation hard.  Then, when all else is still failing, place some kind of scope on your interaction so that you can see what is going on in order to debug it.
    Hope this helps,
    Dan
     
  12. Like
    Commanderfranz reacted to patrick poirier in ARTY running MicroBlaze on FreeRTOS   
    Hello Sam,
    OK the FreeRtos works on the Arty MicroBlaze... You can consider this post closed :-)
    So now I can build a processor from scratch and tailor it to my requirement, it just take a couple of hundred hours of coding, so it is not as easy and fast as uploading a blink code into a 3$ Arduino, but it does what's advertised.
    Thanks
  13. Like
    Commanderfranz reacted to dk_vhd in genesys 2 board not showing up in Vivado HL 2016.1   
    I found the solution at :
    https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/genesys-2-board-not-showing-up-in-Vivado-HL-2016-1/m-p/698807/highlight/false#M13275
    Thanks,
    Dee
  14. Like
    Commanderfranz reacted to Bianca in Digilent Tutorial for Microblaze based system on Nexys Video yields timing errors - How can I fix them   
    Hello jcv65,
    I have followed the same steps in Vivado 2015.4 and didn't get any timing errors. Please try with this version of Vivado. From what I see this could be a Vivado bug.
    Best regards,
    Bianca
  15. Like
    Commanderfranz reacted to AndrewHolzer in data transfer example via ethernet   
    Hello dk_vhd,
    We don't have any sort of examples for transferring data from the DDR to PC via Ethernet. I suggest that you search online for documentation on implementing a C socket server. Because the DDR is actual physical memory, nothing special needs to be done in your C code to write and read data from it. Any guides that you find should help you create a project that doesn't just simply echo data, but is able to create and serve its own data.
    I hope this helps. If you have further questions, don't hesitate to ask!
    Andrew
  16. Like
    Commanderfranz reacted to sbobrowicz in Genesys2 demo project   
    Hi Zygot,
    I hear you, and agree with a lot of what you are saying. But we cannot ignore block diagrams, microblaze, and other IP cores: they provide too much value for our customers. It is very difficult to use many of the components on the Genesys2 in a meaningful way without using an IP core (DDR3, Ethernet, Displayport are examples). On top of that, in many cases properly designing your system around a microblaze processor(s) reduces design-time and results in a project that is more readily adapted to meet future requirements. This type of approach can turn design-time from weeks into hours.
    Understanding that we can't turn away from IP blocks entirely, here are my comments on your other suggestions:
    -When used to generate a project that does not contain a block diagram (even if it does contain IP blocks), tcl scripts actually tend to increase version compatibility. This is because project files cannot be opened in earlier versions, however a tcl script will generate a project for whatever version it is being run in. There are cases when a project creation tcl script can break across tool versions, but this is not as common as you might think. They also greatly increase a project's ability to be properly version controlled, which is necessary for us to be able to successfully maintain them (as is true with all software).
    -tcl scripts that are used to generate block diagrams are version specific. This is very unfortunate and what is behind the headaches you have experienced with our demos. We are implementing a plan to mitigate this problem. First, we plan to update all block diagram containing projects on our github to version 2015.4. Once we achieve this, we will maintain these projects by systematically updating them to the "even" versions of Vivado as they come out. This means that when 2016.2 comes out, we will go through and update each project, handling any conflicts that occur with new versions of IP cores. This will ensure that our projects are all usable in recent versions of the tools, and also that people who only have access to earlier versions of tools (perhaps due to license expiration) can revert the repo and use an older version of the project. Choosing to only do the even versions (.2 and .4 releases) is a necessary compromise to make this task achievable for us. I'd like to hear your comments on this plan, specifically if you think this would have addressed the problems you encountered.
    -When it makes sense, creating a pure HDL project can increase portability between tool versions and hardware (which is particularly useful to us). We do this when we can, typically to highlight simpler onboard components like GPIO, UART, and VGA. But when a project begins to need external memory or have complex state requirements, it begins to make more sense to teach people to do it the easier way, with microblaze. To assist those that prefer to design purely in HDL, we are putting together a library of re-usable HDL components on our github (it's not ready yet). This will contain many of the "reference components" found on our old website, and a revamped collection of useful components such as I2C controllers, UART controllers, etc.
    -I hate it when we are forced to use paid cores, and we do whatever we can to get around this when possible. On the Genesys2, we currently require paid cores to use the USB-OTG, Displayport, and ethernet. Good news on the USB-OTG front, we are about to release an open source USB device core and some example microblaze software to go with it. For ethernet, all we need is a functional GMII to RGMII IP core and that will allow us to use the free ethernet lite core instead of the paid "ethernet subsystem" core. Vivado already ships with such a core, but for some reason it only lists "zynq" devices as supported. We are looking for a way around this. Display port will be the toughest nut to crack, though I recall Hamster (on this forum) mentioning he has successfully gotten display port output functioning in some capacity. 
    -Regarding ISE compatibility, we made the decision to just focus on releasing Vivado projects for the products that are supported in both tools (Nexys4-DDR, Nexys Video, Genesys 2, ZYBO and ZedBoard). We feel pretty strongly that Vivado is a viable replacement to ISE in all regards, with the exception of those who require the schematic capture tool for teaching purposes (though IPI libraries are getting close to being able to replace that need too). That said, you bring up a good point about our lack of UCFs, so I will find some resources to put these together this summer. 
    You mentioned that Vivado 2014.4 does not work with your license that unlocks 2015.4. According to this, that should not be the case:
    http://www.xilinx.com/support/answers/33770.html
    A node locked license is supposed to unlock all versions of the tools that are released prior to the "version limit" date. Are you certain that the "Design Edition" of 2014.4 was installed on your machine? If it was the webpack version, targeting the genesys2 will not work, even with a license installed. 
     
  17. Like
    Commanderfranz reacted to dakefeng in Genesys2 demo project   
    zgyot,
    I am working on it right now, and what do you want as a simplest demo? I will see if I can make one. Are you using Vivado 2015.4?
    Besides, I am still waiting for the board definition file for genesys2.. I think when we have that it would be a lot easier to start a new project.
    Best,
    Dake
  18. Like
    Commanderfranz reacted to Bianca in ZYBO peripherals   
    Hello Sayali,
    Please see the following points:
    chose one designing tool and stick to it. If you still port your project from ISE to Vivado and vice-versa it's normally not to work I recommend you to stick to Vivado because it has more features and the webpack edition is free What you have sent me is a ISE project with an XDC file. ISE works with UCF, Vivado works with XDC If you want to sent the files, please send the source files not the project. (what you have sent is just the beginning of the project and I cannot reconstruct it without the source files) Synthesize your project again in Vivado. and see if your Errors persist. It looks there are just the ports that are different from your files to XDC file.  If you still have errors, please attach the source files and the XDC if you decide to stick with Vivado or the UCF if you want to work in ISE or the whole project in an archive. 
     
    Best regards,
    Bianca
  19. Like
    Commanderfranz reacted to artvvb in ZYBO peripherals   
    Hi Sayali,
    I'd recommend running through the ZYBO Create a Custom IP Core tutorial (https://reference.digilentinc.com/zybo:custom_ip_cores). The Xilinx tools will let you instantiate VHDL designs inside of a Verilog project, so in the step 4, "Add user logic here" section, rather than copy-pasting the PWM code, you should be able to design a VHDL equivalent, and instantiate it. While the project wouldn't be pure VHDL - the AXI controllers would be automatically created for you in Verilog - you would be able to have VHDL between this bus and the peripherals. I haven't seen a way to have Vivado create the AXI controller in VHDL, so I'm not sure this is exactly what you are looking for...
    Thanks,
    Arthur.
  20. Like
    Commanderfranz reacted to JColvin in NEXYS4-DDR FPGA Card in Matlab-Simulink FPGA in the Loop (FIL) connection   
    Hi radres,
    Unfortunately Digilent will not be able to help with this: the Nexys 4 and the Nexys 4 DDR are designed differently so you will not be able to as easily port code from one board to the other. MathWorks creates and maintains those files for Simulink, so they would need to add support for the Nexys 4 DDR.
    Thanks,
    JColvin
  21. Like
    Commanderfranz reacted to mskreen in How to program Arty flash   
    Hello davec,
    You can find a simple tutorial on how to program the Arty using Quad SPI in step 4 of the Arty Programming Guide. Vivado has the option to program the flash with a .bin file using the Hardware Manager. You can consult the Arty's reference manual, section 4.1 for more Quad SPI configuration information. Hope this helps!
    Mikel
  22. Like
    Commanderfranz reacted to JColvin in Nexys4-DDR board files for Matlab-Simulink   
    Hi radres,
    Check out my reply for your other thread here.
    Thanks,
    JColvin
  23. Like
    Commanderfranz reacted to AndrewHolzer in Getting pmod ports into a block diagram   
    Hi Snohomish,
    I was a bit confused at first, because I was having the same issue that you described. I asked around and found out that you'll need to download this repository and follow what the README.md says. I did so and was able to drag a Connector JA component into my block design with no hitch. 
    Try this and please let me know if it works for you or not.
    Andrew
  24. Like
    Commanderfranz reacted to JColvin in Circuit Analysis Question from YouTube   
    Hi chendon,
    I think Dr. Hanshaw worked it out ahead of time. Plus since this was just a lab video as opposed to one of the lecture videos, he presumed that people (in order to save time for each lecture) had watched his previous lectures and knew that he had worked it out via some sort of circuit analysis.
    Thanks,
    JColvin
  25. Like
    Commanderfranz reacted to elodg in DDR3 Termination   
    On the Zybo, a different routing topology has been used (tree vs. fly-by), that allowed for shorter traces and the use of near-series termination, instead of far-parallel.