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  1. Like
    Commanderfranz reacted to bgetz in uc32 GPIO Programming problem   
    Never mind ... stupid programming error...
  2. Like
    Commanderfranz reacted to JColvin in uC32 communication with PC   
    You are correct, you will not be able to use a USB Application library because the uC32 does not have a USB host receptacle on board. There are only two ways that I am aware of that you would be able to control the uC32 from your PC. One is the communicate with the board through the Serial Monitor of MPIDE or the Arudino IDE and have the uC32 preprogrammed to execute different functions when you type different lines of text into the Serial Monitor. You can learn more about this in one of Digilent's blog posts.
    The other way that I know of is that you can actually control the uC32 through LabVIEW. I have used LabVIEW Home Edition combined with LabVIEW MakerHub LINX (following this tutorial to get everything set up; it's for the WF32, but you can choose the uC32 instead) to get a lot more interaction (and more friendly GUI) to control the board.
    Let me know if you have any more questions.
  3. Like
    Commanderfranz reacted to JColvin in PmodOLED display voltage   
    The PmodOLED is configured so that the internal DC/DC boost circuit is used, so it was deemed not necessary to put into the reference manual as the user only needed to make sure they supplied 3.3V to VCC. Otherwise, as per the display datasheet linked in the reference manual, the display needs between 7V and 7.5V with a typical supply of 7.25V.
    I'll see if I can get the PmodOLED datasheet updated to explicitly state this somewhere.
  4. Like
    Commanderfranz reacted to [email protected] in Sending Usb D+ D- signals to Zedboard   
    I guess the answer is ... it depends.  Are you interested in USB3.0, USB2.0, or USB1.1?
    Let's assume for the moment that you are interested in USB3.0 with a 5GHz clock.  (I think it's actually 5.12GHz ...)
    I can see a couple of basic approaches.  The first is to try to capture the signal with a 1-2 bit A/D converter running at over 10GHz and asynchronous to your design.  Find a chip that can do this, and then ingest into your design at the clock rate you wish to use ... I don't have suggestions regarding what would make this work, but it could be made to work.
    Another approach would be to try to synchronize with the USB data.  This would allow you to drop your requirement to 1-bits at 5GHz.  This would get you closer to the rate you can ingest.  The easiest way to do this would be to add a USB processing chip (PHY) to your design.  I'm not sure, however, if this is within your requirement set ... are you trying to debug a non-functioning USB port?  If so, adding a PHY won't reveal why the port isn't working.
    I suppose a third approach might be to limit the USB speed to something much lower, say USB 2.0 speeds (480Mbps).  Here you might manage to use a series-7 ISERDES capability within your chip to bring in the data at a reasonable clock rate.
    If you drop even slower, say to USB 1.1 speeds, you can find a USB 1.1 PHY in VHDL here.  That might give you some ideas as to where you might go for higher speeds.
    Hope this helps.  If not, please help me fill in the gaps: do you want a PHY, or a simple recorder/analyzer?  What USB speeds are acceptable?  etc.
  5. Like
    Commanderfranz reacted to [email protected] in CMOD S6 JTAG   
    Depending on what you need, it is possible to reconfigure a board without the JTAG port.  For example, you could use one configuration to load a new configuration into the flash and then switch to it.  You could even control the first configuration and program the second via a UART port or ... gosh, just about any communication port you can connect to the CMod.  I've done this through UART, JTAG, and DEPP interfaces, so I know it can be done.  Indeed, the original plan for my CMod S6 SoC was to use the UART to do this.  In the end, the DEPP interface was just too easy to use, so I dropped the requirement to do reconfiguration via UART.
  6. Like
    Commanderfranz reacted to hamster in NetFPGA incorrect Ethernet PHY pins   
    If that is a RGMII, that pin should be an output not an input. The best reference I have found for RGMII is
    Rather than muck about (or maybe more accurately "rather than actually learn") how output delays work, for my design, I generate it using a DDR register that is fed with a clock that is at 90 degrees to the main design's clock.
    Some PHYs have the option to introduce a skew into the transmit clock,, and some designs achieve this though using a longer trace length for the clock line (this seems a bit dumb to me, but if needs must).
  7. Like
    Commanderfranz reacted to [email protected] in Output voltage levels from the FPGA development boards   
    Perhaps the safest way would be to use a logic level shifter, such as this PMod.
    A cruder way, if you only need to go from 3.3V down to 900 mV is to put an appropriately sized resistor between the two.  For this, I'll say that 1) No, I don't know the value, and 2) on the last project I was on where someone used this technique the result was ... a mess.  So I know it is doable, but I've never done it.
  8. Like
    Commanderfranz reacted to hamster in UART in nexys3 by VHDL   
    On second glance you are setting INDEX back to zero, just not where I expected in the "IF (TX_FLG='0' AND START = '1') THEN" block.
  9. Like
    Commanderfranz reacted to hamster in UART in nexys3 by VHDL   
    I think I see your problem.... do you ever set INDEX back to zero?
    It might be easier initially to send additional 1 bits after the data to simplify things.... e.g. 0,a,b,c,d,e,f,g,h,1 and then 22 '1's (where the letters are your data bitsfrom the switches), and just repeat that over and over. Just have INDEX counting from 0 to 31,
    You can then enhance that only send when the key is pushed (e.g not rolling from 31 back to 0 unless KEY='1', and then speed it up by sending fewer extra bits, until you are running at full speed.
  10. Like
    Commanderfranz reacted to [email protected] in How to use the on board 16MB memory of nexys 3 via VHDL. Any help is appreciated .   
    You can actually find several different examples in the XST manual for how to implement block RAM.  There are several subtleties to be aware of, such as if you are reading and writing the same address on the same clock, which result will be read?  The new one or the old?
    (I was actually going to post the Verilog example code from the XST manual for what jpeyron posted above, but ... then got lost in the details and subtleties and figured I'd just post a link.  )
  11. Like
    Commanderfranz reacted to jpeyron in JTAG HS2 Letter of Volatility   
    I have attached the Statement of Volatility for the JTAG-HS2. 
    thank you,
  12. Like
    Commanderfranz reacted to Bianca in Is there an arty drawing available?   
    Hi Gra,
    Please see the document attached.
    Best regards,
    Arty Dimensions.pdf
  13. Like
    Commanderfranz reacted to JColvin in Programming a Kintex-7 with JTAG HS2   
    Hi daumanec,
    I talked with some of our application engineers and yes, you can use the JTAG-HS2 to program your board. I only asked about the Digilent boards because they already incorporate the necessary programming solution that is present on the JTAG-HS2.
    Let me know if you have any more questions.
  14. Like
    Commanderfranz reacted to JColvin in Questions about the AD2   
    The software for the Analog Discovery 2, WaveForms 2015, is Windows, Mac, and Linux compatible. You can view more of the OS details on the Waveforms Resource Center. So, you likely will need Windows installed on your tablet (as opposed to Android) to get Waveforms running. I don't know how the user interface on a tablet compares to that of the desktop version.
    The housing on the AD2 is 8.2 cm long (and wide) at the corners and is 8 cm long (and wide) in the middle. You can remove the housing and take advantage of the 6 mounting holes in the PCB. The PCB itself is is 7.5 cm long on both sides.
    Let me know if you have any more questions.
  15. Like
    Commanderfranz got a reaction from EllaRickerson in Xilinx Roadmap on XC9500XL CPLDs   
    Hi Romain145,
    Unfortunately we can't speak to Xilinx's road-map for their products. I would recommend posting on the xilinx forum to see if they can let you know. 
  16. Like
    Commanderfranz got a reaction from EllaRickerson in Rename Failed in WaveForms 2015   
    I'm trying to rename my Analog Discovery 2 in WaveForms 2015 3.3.3 but have been unsuccessful. When I type in a new name it says "rename failed." This seems to happen no matter what I name it, just letters, letters and numbers, and with special characters.  
    I am working in Windows 8.1
  17. Like
    Commanderfranz reacted to FlyingBlindOnARocketCycle in Basys3 Xilinx University Lab 3 - No led's   
    It is functioning in 2015.4 also.  Odd about the problems with 2016.1.  There appear to be problems with usb/serial driver and 2016.1 also.  I seem to be able to have multiple version of Vivado installed and can open the version I need. 
    Thanks a lot for all the effort to this issue.
  18. Like
    Commanderfranz reacted to Sergiu in How to display image from FPGA ??   
    I think the demo project for the Genesys2 would be a good place to start. You can find all the information about it here. 
  19. Like
    Commanderfranz reacted to attila in Nexys2 Cypress eeprom iic file request   
    You can use the repair application or the iic file you got in message.
  20. Like
    Commanderfranz reacted to Sergiu in I want to blink LED   
    Please look at this forum thread. You can download the Genesys2 XDC from here. You can build a Vivado project using the code I attached in the older post and the XDC from our wiki. Let me know if you are having difficulties.
  21. Like
    Commanderfranz reacted to attila in Analog Discovery 2 not detected In Waveforms 2015 on Linux   
    Do you have Adept Runtime installed from targz or have some Xilinx tools installed ?
    This could be in conflict with the RPM runtime.
  22. Like
    Commanderfranz reacted to JColvin in LabVIEW Home Bundle 2014 comparison to other editions of LabVIEW   
    Hi derjape,
    It explains in the video on LINX Software setup page (around the 1 minute mark) that the LabVIEW Home Edition has since been updated (within the last few months) to include the Application Builder with it. If you have installed LabVIEW Home previously, you will be able to right click on the Application Builder and activate it without having to re-purchase LabVIEW Home Edition.
    Naturally, Digilent doesn't have any control over the NI page on LabVIEW home, but I see if Digilent can update our own page to reflect this.
    Let me know if you have any more questions.
  23. Like
    Commanderfranz reacted to Bianca in Cmod S6 Physical Dimensions   
    You have here the dimensions of CMOD S6.
    Best regards,

  24. Like
    Commanderfranz reacted to [email protected] in UART CODE   
    Oh, here's another one for you: the wbubus.v component of the XuLA2 SoC converts character data into wishbone bus commands.  So, if you want to control 32'bit registers, with 32'bit addresses, both reading and writing, that'll do it for you.  (The host software half to the same thing can be found in ttybus.c.  On my Basys3 I drive it with the UART ports, on the XuLA2 I drive it from the user JTAG command, and on the S6 I drive it from the DEPP interface)  I use the same thing on my Basys3 board, as well as on my CMod-S6--but only when the CMod isn't running a CPU as well.  What's more, using this interface, the CMod S6 project also has examples for reading/writing the flash memory.  The flash memory example was also originally generated, tested, and proven on a Basys3 board and only ported to the CMod S6.
  25. Like
    Commanderfranz reacted to JColvin in Adding the Arty board to Vivado   
    It sounds like you need to add the Digilent board files to Vivado. You can follow our guide that we have on our Wiki here.
    Let me know if you have any more questions.