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  1. Like
    Commanderfranz got a reaction from TamasK in Why Kaitlyn stopped doing humorous videos on YouTube?   
    Hey Paolo,
    I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. 
  2. Like
    Commanderfranz got a reaction from JColvin in WaveForms Live Update: New Features!!   
    Hey All,
    We recently posted a new version of WaveForms Live which ads some new features. This blog post lists all the changes in the update. 
  3. Like
    Commanderfranz reacted to AndrewHolzer in OpenScope and OpenLogger log file utility - export to CSV   
    Hi all,

    Quick update here. I've got binaries built for Mac and Linux (Ubuntu) and have updated the documentation to link to them. You may also download the Windows, Mac or Linux binaries by following the links I just gave you. If you encounter any issues whatsoever, submit in issue on the GitHub page and I'll set to fixing them straight away.

  4. Like
    Commanderfranz got a reaction from [email protected] in Why Kaitlyn stopped doing humorous videos on YouTube?   
    Hey Paolo,
    I'm glad you found my videos helpful! I've been working on other projects, but if you have any other ideas for videos that you would find helpful let me know. 
  5. Like
    Commanderfranz got a reaction from sbobrowicz in Vivado and Windows 10 Fix   
    There are two ways to fix this, rename C:\Xilinx\Vivado\2015.2\tps\win64\xvcredist.exe to anything else, or add the line "set XIL_PA_NO_REDIST_CHECK=1" after line 115 in C:\Xilinx\Vivado\2015.2\bin\loader.bat.
  6. Like
    Commanderfranz reacted to JColvin in WaveForms 3.6.8 release   
    But in this particular case, just props to @attila since as far as I know, WaveForms 2015 == attila.
  7. Like
    Commanderfranz reacted to Dirk in Learning Edition   
    Thank you. Very nice kit... 
  8. Like
    Commanderfranz reacted to Bianca in Possibly faulty Nexys Video   
    Hi Wolf0,
    The thing you are encountering is not a bug, but the limitation of the design. When you have a very large project that would take a large part of the FPGA capability and at a high frequency the FPGA starts consuming power. If it goes above the maximum current the source provides, the board resets. In the board reference manual you can find a table of what the power sources care capable to supply. Vivado can estimate the power consumption of your design. You can check that and compare it with the values provided in the table of the power sources. If the value provided in Vivado is higher than the value in the table, there's the problem. 
    Best regards,
  9. Like
    Commanderfranz reacted to Bianca in Joseph   
    R254 is a 0 ohm resistance. you can find it on bottom of the board. See picture attached. It is true though, that it has a tolerance of few miliOhms. They are not different from one board to another.
    Best regards,

  10. Like
    Commanderfranz reacted to oe7aft in Arty & Microblaze bootup from Flash   
    Thanks Andrew,
    in the meantime great step-by-step Tutorials on this topic have been made available here (under "Documents" ) and here and I have been able to store the application program on flash.
  11. Like
    Commanderfranz reacted to Bianca in Max Supply current of VDD(VREF) in JTAG-HS2   
    The FTDI chip is powered by a 5V power supply that can provide a maximum output current of 300mA. The reference voltage of 3.3V is provided by the FTDI chip itself and can provide a maximim of 60mA
    Best regards,
  12. Like
    Commanderfranz reacted to [email protected] in Nexysvideo and Adept   
    I have always read the content of the flash off any of my devices before programming them.  I do this because I am loathe to program over and on top of the flash, while losing something that I had originally purchased.
    You can find a Verilog example of the QSPI flash controller I use here.  You'll even find a C++ simulation there that is valid for many (most) QSPI flash devices.
    One of the difficult parts of such a project is making sure that you can read from, write to, and in general communicate with the FPGA.  I like to use an internal wishbone interface within the FPGA, and so the first requirement of using any of the routines I suggest is that you can command reads and writes of that wishbone bus.  I abstract accesses to this interface via what I call a devbus.  The purpose of this abstraction was to make certain that programs I built for working with the FPGA would continue to work no matter what the communications layer and protocol was underneath them--whether it be UART, JTAG, DEPP, or even PCIe.
    You can find examples of projects where I've done this here (for an Xess XuLA2-LX25), and here (for a Digilent CMod-S6).  I've also done this with a Digilent Basys-3 board (code not posted).  In the XuLA project, the wishbone is commanded via a JTAG interface.  I use a DEPP interface for the CMod.  Today's task has been working to do the same for Digilent's Arty board--I'll be using a UART to command that interface.  While I have never done this with the Nexys Video, I have to believe most SPI flash devices are fairly similar.
    Sorry this isn't a point and click solution for you, but it should be something that gets you closer to a solution.
    Let me know if you have further questions,
  13. Like
    Commanderfranz reacted to Dwayne in Voltmeter in WaveForms 2015   
    Commanderfranz,  the Data Logger does work as a voltmeter, however I find the Scope Measure function under View very helpful as well.  The Scope section seems to have all of the features comparable to a Keysight USB or Tektronix digital storage oscilloscope.  Very impressive.  The data display seems better than a Fluke 190.  It is, of course, lower in voltage and frequency range than the other devices mentioned, but also far less expensive. The voltage range can hopefully be extended with a 10:1 'scope probe and the adapter.  The sampling and processing is lower, of course, so there are a few 'scope display anomalies. However, this is more than acceptable for home hobby, or even low frequency circuit troubleshooting, as far as I can see.
    The Spectrum display also seems to work nicely, as well.  I'll see if I can set it up to measure some Bessel nulls later when I try the FM function.
    I'll be checking out the signal generation in more detail on some later projects.
  14. Like
    Commanderfranz reacted to JColvin in Cmod A7 DIP Footprint   
    Hi Leonardo,
    The CmodA7 has a standard DIP footprint, so the two rows of pins are 0.6 inches apart with 100 mil spacing between each of the pins along the rows.
    Let me know if you have any more questions.
  15. Like
    Commanderfranz reacted to Bianca in Cmod A7 oscillator question   
    Actually the CMOD A7 has two oscillators a 12MHz and a 100MHz. If you look in the schematic, there is a black page. There is the 12MHz clock but we cannot release that page. You can find it on your board listed as IC8. The 100MHz clock is GCLK that goes to the bank 14 of the FPGA and is used for applications requiring a very fast signal connection.
  16. Like
    Commanderfranz reacted to Bianca in New ARTY board, project question   
    You should generate the program with the Vivado version it was compiled. If not, Vivado will make an upgrade of the project that may or may not work. 2016 versions of Vivado are not very stable and your design might fail. We had previous problems with Vivado 2016 on projects for Nexys4-DDR or Genesys2. 
    Best regards,
  17. Like
    Commanderfranz reacted to BKallaher in Cmod S6 toolchain?   
    The Spartan 6 series is not supported by Vivado. The tool to use for the Spartan 6 is ISE. You can find the download for ISE at this link:
  18. Like
    Commanderfranz reacted to saleksin in ZedBoard Linux Hardware Design for Vivado   
    Thanks for the reply! is obviously the first place to search. Unluckily, many of tutorials, or designs are out of date (for example they are from ISE days), or consists of cores, that are not available at no cost. Reference design is the one from first group.
    The second page is also familiar to me, but has nothing I need in this case.
    But actually, I've found the solution. It is here: There should be link to this page on instead of old version that is posted. This reference design has almost every component or interface that is on the board, including OLED and in my opinion it is the best start point for other designs.
    Now my problem is that I can't get OLED kernel module work. It works, when I compile it as built-in driver, but this way I was not able to launch poweroff sequence, which AFAIR is important for OLED module. So I will be happy to see some example for Zybo, as It will be almost the same for Zedboard.
  19. Like
    Commanderfranz reacted to Bianca in I want to blink LED   
    Hello hilarikas,
    I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file.
    Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. 
    XDC syntax for the clock:
    ## Clock Signal
    #set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
    #set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
    UCF syntax for the clock:
    ## Clock signal
    #NET "clk"   LOC = "E3"    | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF)
    What you tried to do:
    ##NET "refclk" LOC = "AD11";
    Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this:
       generic map (
          DIFF_TERM => FALSE, -- Differential Termination 
          IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
          IOSTANDARD => "DEFAULT")
       port map (
          O => O,  -- Buffer output
          I => I,  -- Diff_p buffer input (connect directly to top-level port)
          IB => IB -- Diff_n buffer input (connect directly to top-level port)
    Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this:
       generic map (
          DIFF_TERM => FALSE, -- Differential Termination 
          IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
          IOSTANDARD => "DEFAULT")
       port map (
          O => refclk,  -- Buffer output
          I => sysclk_p,  -- Diff_p buffer input (connect directly to top-level port)
          IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port)
    After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal.  Attached to this post is a word document with a tutorial on how to assign the clock.
    At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this:
    create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p]
    After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. 
    Best regads,
    Asign Clock.docx
  20. Like
    Commanderfranz reacted to JColvin in Vivado schematic capture   

    Xilinx's Vivado Design Suite does not support schematic entry. If you happen to have schematic files from Xilinx's older ISE, you can convert those into HDL code as described in this thread on our technical forum.   Otherwise, the only other product that Digilent sells (but does not make) is the NI Multisim Student Edition, which does support schematic capture and can also export digital logic designs into VHDL. However, as Digilent only re-sells Multisim, we are not able to offer proper technical support for it so any technical questions you have about it would need to be directed to NI's forum. I also want to point out that NI does have some tutorial material available for Multisim here.   Let me know if you have any more questions.   Thanks,
  21. Like
    Commanderfranz reacted to [email protected] in Maximum flash speed   
    Thank you for the encouragement!  I think I will do just that: I'll test the bounds of how fast I can get a controller to go, and post the results back when I have them.  My goal will be to get it up to 100MHz, and I'll let you know how close I get.
    But, yes, like you said, one of my motivations is to use the SPI as an active ROM memory for my project and, when doing that, the faster it goes the faster everything else can go when using it.
    Who knows, perhaps you'll want the HDL I put together so that you can test your next board and see if the SPI can be made to run at 100MHz?
  22. Like
    Commanderfranz reacted to [email protected] in Enjoyed listening to Clint on The Amp Hour   
    One thing I find surprising, but perhaps should not, is how focused Digilent's roots are in the academic community.  I guess I had always seen it as a sort of low-end demo-board outlet for Xilinx, rather than a company whose purpose from the beginning was to supply student usable parts for computer engineering work.
    The whole discussion of pricing was quite fascinating as well.
    Finally, I really enjoyed Clint's encouragement to get into the weeds and actually build things.  I know from my standpoint, I was always frustrated when I tried to study communications systems that the comms classes I took never taught the tools necessary to really build things: phase locked loops.  It was fascinating to hear, in the audio, the same sentiment expressed by the host for learning to build circuit boards and never teaching how to understand power supplies.
    I guess I have a long way to go, but it was nice to be encouraged,
  23. Like
    Commanderfranz reacted to hamster in Enjoyed listening to Clint on The Amp Hour   
    I case you haven't heard it already check out an interview with Clint Cole (one of Digilent's founders) on The Amp Hour.
    The company history sounds very different than I imagined it was...
  24. Like
    Commanderfranz reacted to Allan Flippin in Question about FMC connector on Nexys Video board   
    Thanks JColvin and Bianca.  Yes, I had searched online for that part.  I noticed a few sources, but all in the UK and none in the US.  That doesn't bother me, except I thought perhaps the connector was being phased out.
  25. Like
    Commanderfranz reacted to Bianca in Question about FMC connector on Nexys Video board   
    DigiKey had the connector but now it's currently out of stock. You can find it at Farnell
    or you can search on other online shops: The part number is ASP-134603-01 and is produced by Samtec.
    Best regards,