Commanderfranz

Technical Forum Moderator
  • Content Count

    225
  • Joined

  • Last visited

  • Days Won

    9

Everything posted by Commanderfranz

  1. Hi grf, This question has been escalated to someone who can more accurately provide you with an answer. Kaitlyn
  2. Hi JasonT, I have escalated your question to someone who can more accurately answer this. Kaitlyn
  3. G. Singh, It sounds like you are either having a driver or software incompatibility issue. Here are the release notes for the version of ISE you are running. I would recommend checking to make sure all the OS and processor requirements are met (page 7), and checking out the driver installation guide (page 11). I've had issues with drivers appearing to install correctly, when really they didn't, so its always worth a shot. Hope this helps! Kaitlyn
  4. Hi Alex, I'm am not at all suprised that the Nexys 4 DDR takes longer in implementation and bitstream than does the Spartan 3. The Nexys 4 has an Artix 7 FPGA rather than the Spartan 3 FPGA. The Artix 7 is a much larger and more complex FPGA so that software has more configuring to do than on the Spartan 3. As far as the specific times he gave, for a fairly complex design around 4 minutes on an i7 is not at all surprising. If he tells me which sample project I can tell specifically if this is expected. As far as settings go to shorten the build time, I would recognize posting on the Xilinx f
  5. Hi Mihai, Can you post a link to the example you are referencing? Kaitlyn
  6. Roger_S, The JTAG-USB cable can be used with Digilent Adept, which is a free software download. Kaitlyn
  7. Hi Bolt, I'm sorry you're having such a hard time! I don't personally have an experience with this specific Vivado issue so I don't have any tips for you. I would recommend posting on the Xilinx forums as they produce the software and will be better suited to solve your issue. In the mean time I will escalate this to the applications team and see if any of them have seen this issue. Kaitlyn
  8. Hi ASD, I'm sorry you're having trouble. Here is the newest version of the tutorials. Kaitlyn
  9. Hi Gazi, I'm so sorry you've hit so many obstacles! According to what you listed you tried, it should work. I'm going to list all of the trouble shooting steps I would take anyways just in case something is slightly different. Sometimes the smallest thing can make a difference. Using the correct cable: Many USB cables only work for power, make sure you are using an actually programming cable Re-installing Cable drivers: I found 3 different solutions for this on the Xilinx website. Xilinx Cable Drivers Digilent Cable Drivers All Cable Drivers re-installing the hardware server Since
  10. Commanderfranz

    Basys2

    Serge1983, Jonathon in correct. Adept will not synthesize your code, but it will only download the bit file to the board. The problems you are facing with synthesizing your code is likely because Vivado does not work with the Basys 2. You will need to use Xilinx ISE to Synthesize and implement your code for the Basys 2. You can simulate the code on Vivado because this is not reliant on which FPGA chip you are using. However, you can also simulate your code in ISE so you do not need Vivado. As far as using adept on Linux I would recommend you check out this post. Hope this helps! Kaitlyn
  11. Hi Jonathan, You are correct, input and output types by default are wires. Only if you use the keyword reg with they change to a register type. Saying output wire isn't wrong, but is redundant. Hope this clears things up! Kaitlyn
  12. Hi there Digilent Studio, I can certainly see the confusion there. In the earlier section the feedback loop has only one possible loop. Through the +ve terminal of the opamp through the resistor and connected to the output of the opamp. However, in the second circuit you discussed there are two possible loops for the feedback loop. Yes it does connect to the positive terminal of the opamp, but it also connects to the loop going through the resistor and Vin. So, although there is still no current into the opamp, the capacitor has current flowing through it, because of the other path. I hope th
  13. Drew Locke, Before you decide to use FPGA's I would recommend you check out the learn site modules, or XUP site on FPGA design. That way you can decide if FPGA design is right for you. Looking more into your design it looks like you'll have, 5 servos for ingredient control, A pressure sensor for each ingredient, so 5, a port for the display, and USB for the keyboard and mouse. The ZYBO would certainly be able to do the calculations but I'm not sure if it is right for the amount of peripherals you have, at least 13. I would highly recommend you decide what peripherals you need before deciding
  14. akhil, Can you also tell me which voucher it was that you got from Digilent?
  15. akhil, Can you send me a screenshot of what shows up when you are in the license manager under view license status? Kaitlyn
  16. Hi Gary, I'll try to get you as much information as I can to get you in the right direction, but once you know the Xilinx FPGA and your asking about Xilinx IP's this is more of a Xilinx question. All you need to program the Nexys Video is Xilinx Vivado. There is a free version of Xilinx Vivado called the Webpack edition. Here is a chart that shows the different versions. I searched for a Xilinx FFT IP and found this page. It looks like they have a FFT IP that is compatible with the Artix 7, and it comes with the Vivado Design Edition, which is not free. I'm not sure how purchasing IP's works
  17. Hi BlackKnight, I added this note: Note: The Analog Discovery BNC adapter board does not have differential analog (scope) inputsto the wiki for the BNC adapter and sent in a webpage change request to add it to the product page. Kaitlyn
  18. Hi Marcel, The example in the text book is a closed system, therefore to apply efficiency is misguided as efficiency is always the same in a closed system, because Pout = Pin in a closed system by definition. Even if I applied efficiency to this circuit it would go as follows. The conclusion in the textbook states that RL = RTH for maximum power transfer. Since RL and RTH are in series their currents will be the same, that is IL = ITH. Efficiency is defined as Pout/Pin. Pout = RL(IL)2 since the load is our output. Pin = RTH(ITH)2 since the source is the input. Thus efficiency = (RL(IL)2)/(RT
  19. Hi Shahabamo, I would recommend trying to program with Digilent Adept. It is a free software. Kaitlyn
  20. Alex and skyberrys, After reading through the Nexys 4 reference manual it doesn't look like the Pmod Connector VDD pin can supply any voltage other that 3.3V Kaitlyn
  21. Priya, I can't help you without the .v .vhdl and .xdc files. I need to see the actual code in order to figure out whats wrong with it. Kaitlyn
  22. There are two ways to fix this, rename C:\Xilinx\Vivado\2015.2\tps\win64\xvcredist.exe to anything else, or add the line "set XIL_PA_NO_REDIST_CHECK=1" after line 115 in C:\Xilinx\Vivado\2015.2\bin\loader.bat.
  23. A lot of people haven't been able to upgrade to Windows 10 because Vivado will stop working.
  24. Hi 0928090, You are correct. I found this page that lists all of the AXI Stream IP's. Take a look and see if you find what you are looking for. If not I would recommend posting on the Xilinx forums, since this is about the Xilinx software and not about the board. Kaitlyn
  25. Thanks Hamster, I will make a new thread for this fix as well I just wanted confirmation. Kaitlyn