coldfiremc

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  1. Check logs and implemented design to see if the block is optimized/deleted in some way
  2. I finally managed to interface this device. I used lots of documentation, but the most informative was the altera AN433 Application note, that details how to write and derive constraints to modify the STA behavior to time this type of devices properly. Thanks @zygot
  3. Ok I found something Interesting Despite the board file has the I/O pins defined for this interface (and an associated IP), Implementation fails because i/o pins are not fixed. This is very strange considering that to assign a pin explicitly is enough to fix the I/O mapping. This is the error (The ISERDES needs an explicit and fixed mapping) Here's the "anomaly" I will check this further, digging in the Board File. Probably it needs a little fix Greetings
  4. After developing a project with this board I noticed that this problem is not only affecting the DVI input IP, but also the clock wizards. Apparently the board file has some inconsistent names. Also the constraints for this IP are a little "Weak" and with a minimum modification, are not applied correctly. Please update the board files. A workaround for this is write constraints manually, but this is not always easy for block designs. Also there's other problem with rgb to DVI, input frequency is not updated accordingly, so this error appears [BD 41-927] Following properties on pin /r
  5. Hi I'm trying to use the RGB to DVI ip to acquire video, and I'm getting placement errors. if I unpackage IP, I, can't find any "conflictive" setting related to placement, in the sense that there isn't any physical pin reference at all and ISERDES instances look good. I'm providing the 200mhz ref clock to properly drive input delays and I'm not using any external constraint file. How can I fix or check that there isn't anything wrong? The board (and related configuration) being used is a nexys Video, and compiling with Vivado 2021.1. The rest of the design has a microblaze, some button
  6. RGB to DVI is just about the physical interface and not the video signal itself. AXI4-to-video IP in fact supports interlaced video. The important part is to calculate properly the timings and setting a proper serial clock for HDMI with an external clock manager. You have to check if your FPGA has enough resources to do this, knowing that HDMI serial clock is a little high.
  7. Hi I have to interface an ADC for a project, and this ADC(ADS4225) fits the requirements. I'm planning to buy the development board and the needed adapter to connect it to the FMC port of a Nexys Video. However, I never interfaced a high speed DDR LVDS device before, and this device (and all of its class) need some signal adjustments to get the data links properly aligned. Can I get some guidance to implement input delays and DDR clock calibration? Thanks
  8. coldfiremc

    Nexys Video HDMI

    I think that this could be a better approach. However, if you want a more clean board you can buy one of those Trenz Electronik SOM's and snap it in a sort of motherboard for your application. With nexys video you can develop the inner parts of the system and then go for the final model with some of those SOM's. This is in the pricey side, but you will end with a more professional "workflow" and a cleaner product. Also SOM's are cheaper than development boards because the absence of connectors and peripherals.
  9. coldfiremc

    Nexys Video HDMI

    It's clear that this cannot be "sufficiently safe" for a commercial design, even considering that the high clock is going into the OSERDESE2. It would be great to hear an "official" answer from Digilent. It's also obvious that clocks in this board are some sort of limited by size/cost/application.Also It's worth to note that the OSERDESE2 implementation is using DDR, that's a pretty neat trick to get the objective frequencies, especially considering the serial clock. Most of this pricepoint boards can't even get 720p running with standard timings. This board struggles to get it, bug it gets
  10. coldfiremc

    Nexys Video HDMI

    Download "vivado-library" and the constraints repo. Nexys video has its own ip to get hdmi output based on oserdese2, its source code is available in the IP itself. It's called "rgb to DVI". It's enough to get 1080p withut problems. You have to put a clock wizard with pixel and serial clocks to make it flexible for any hdmi or DVI mode. I Have a "bare bones" design to get video from hdmi with that. I will upload it to my repo soon
  11. https://opsero.com/product/ethernet-fmc/ check that. buy any board(ie, zynq or nexys video) with FMC, and put that in. Is still pricey?:YES. but a board and this module, Is $500 less than the cheapest net-FPGA. Obviously, this is probably not "the best price" so, keep looking for similar products
  12. Hi, I'm joining this forum to make some questions about your boards. I've acquired recently a Nexys video board. Also I would like to learn something trying to help others with their questions. Thanks