jotran00

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  1. jotran00

    ModelSim Vs Isim???

    Hi, thank you for the responding. In order to get the expected result, I do need the Aldec Active-HDL simulator software in the system. Thanks, Jonathan T
  2. jotran00

    ModelSim Vs Isim???

    Hello, I myself performance some labs in the "Digital Design Using Digilent FPGA Boards" Verilog / Active-HDL Edition (Digital Design, 2nd Edition) book. Many Simulation pics have been seen on this book. Do these pics come out from the standard of ModelSim software?. It is so strange to me in comparing between my result and the result from the book on the same program because I use the Isim (from ISE) to simulate my program. Thanks, Jonathan Tran
  3. jotran00

    Verilog - Data Type

    Hi Kaitlyn, Thanks you for clarifications. Thanks Jonathan Tran
  4. jotran00

    Basys2

    Installed ISE Design Suite 14.4 Ver and it worked fine for Basys2. More the synthesize of codes, is it creating the errors after synthesized codes?. If so, it might be the ISE (Integrated System Environment Software). Another possible situation, is it creating any warning after synthesized codes?. If so, it could be your source codes. Hope this helps, Jonathan Tran
  5. jotran00

    Basys2

    Hello, Adept does not performance anything about the synthesize vhdl codes and it supports to download the file.bit and execute it on FPGA board. If your codes do not synthesize, please check them again and not from Adept. I never heard about the Adept runtime. Please share it if you know.
  6. jotran00

    Verilog - Data Type

    Hello, Have you seen anywhere and experienced the data types below in Verilog?. input wire; output wire;Per my understanding, both input and output data types themselves are wire already. Please correct me if I am wrong. Thanks, Jonathan Tran
  7. Hello, Thanks for your responding. Your formation above helped me more understanding about the functional clock on a FPGA board. I can see the different between clock as the time carrier and the signals as the data carrier that drive over many sets of components on FPGA board. Thanks, Jonathan Tran
  8. Hello, I appreciate if you could help me to answer the following questions: 1. Regarding the clock pin for Basys2 board configured, what is the "CLOCK_DEDICATED_ROUTE" ? and Why is it's setup to "FALSE" condition?. 2. What is the different between the ("NET "mclk" LOC = "B8";) and the ("NET "mclk" CLOCK_DEDICATED_ROUTE;) Thanks, Jonathan Tran
  9. Hello JColvin, Your info above cleared and helped me understanding the different of primary and the crystal (second) oscillator per Basys2 FPGA board. Thanks a lot, Jnt
  10. Hello, Per my understanding, primary ("mclk") and the secondary oscillator ("uclk) connect to PIN ("B8") and PIN("M6") respectively. Could you please explain the different between these two clocks?. Thanks, Jonathan
  11. jotran00

    Website Issue

    Hello, This website issue is resolved and work for me. Thanks for your supports Jonathan Tran
  12. jotran00

    Website Issue

    Thanks Jonathan Tran
  13. jotran00

    Website Issue

    Hello, I can open the main page of the website (https://learn.digilentinc.com/), but I could not access the "Browse Individual Projects" pages further. Could you please check your website?. I love this website because it provides many instructions and helps me to program on my FPGA board. Thanks, Jonathan Tran
  14. Hello, Are the Basys 2 and the Basys 2 Spartan 3E FPGA boards the same?. Also, I saw you have a lot of labs of the Basys 2 board's requirement in both the Digilent website and the "Real Digital - A hands-on approach to digital design" text book. I would think if I buy the Basys 2 Spartan 3E FPGA board for my class at University of Calfornia at Irvine and use this FPGA board for the labs on your website and the text book "Real Digital - A hands-on approach to digital design". If I do this way, I can save cost for buying the FPGA board. Have the great holidays, Jonathan Tran
  15. Hello JColvin, Thank for the good explained of your previous responding. If I buy the lab book of the "Real Digital - A hands-on approach to Digital Design", could I have enough available ports if I use the Spartan-6 FPGA to do some or all exercise in this lab book?. Thanks