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About Erickson

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  1. I have a new design coming along that will need to use I/O pins on the (normally not populated) J1 connector. I don't have easy access to a CORA at the moment, so am looking for X and Y offsets from J1 to the J4/J5 connectors. Also, are there part numbers or height measurements available for the normally populated headers to help in selecting a part with appropriate dimensions to install in the J1 position? Thanks!
  2. Thanks for the input. I suppose the VHDL or Verilog approach would require a little more design-entry work overall on my part, but would make the block diagram a little bit cleaner and easier to follow. For this project, I don't think it makes sense to go down that path, but in the future if I need to add some VHDL/Verilog-defined modules anyway, then I'd want to do this.
  3. I'm working with a CORA Z7 board and developing a system that will use make on and off-chip connections for the GPIO interface via the EMIO. A conceptual block diagram of what I am trying to put together is shown below: I will have a 16-bit wide constant IP block in PL that holds version information to be read-only as seen by the PS, along with a 2-bit wide pair of lines from the push buttons, and finally a 6-bit wide group of outputs to drive the LEDs. My (working, now) solution involves a concat and a slice block in addition to the constant and processor subsystem blocks:
  4. Hi @jpeyron, This is exactly what I needed. Thanks!
  5. Hi Jon, Thanks for the reply. We've already taken caliper measurements here. I'm looking for a DXF file to hand off to a PCB designer to help with placing board-to-board connectors for a custom hat/shield. Is it correct that the outer headers are the same as an Arduino Uno? I think I could track down an Arduino DXF without too much difficulty. Thanks again!
  6. Are there DXF or other mechanical CAD files available for the CORA Z7 board?
  7. I ran some experiments to figure out how much delay is needed. It's somewhere in between 0 and the amount of time added as a result of FSBL_DEBUG_INFO being defined in fsbl_debug.h. I'm a bit of a novice with C, and didn't realize that if I defined FSBL_DEBUG_INFO in fsbl.h, that it would be ignored by the compiler. Had I enabled it correctly to begin with, I probably would have never noticed the sensitivity to delay and would have had a painful time in a few months when we go to do customer demos and I (hypothetically) un-define the FSBL_DEBUG_INFO flag. On a related note, I found
  8. Hi @jpeyron, Before I saw your reply, I went ahead and added a for loop to the start of the FSBL main function, and re-generated my programming files. Now, from the time I reset the board until the done bit LED comes on is several seconds. I was pleased to see that my helloworld program now executes correctly. It appears I stumbled upon an additional issue that may have been confusing things for a while. When I power cycle the CORA board, Tera Term seems to disconnect from the COM port, even though it continues to read "COM4:115200baud - Tera Term VT" at the top of the window. Do
  9. Hi @jpeyron, Both SD cards that I tried were formatted to FAT32. Unfortunately, I can't provide a screen shot of the contents. I can't connect an SD card into a work computer system, due to an IT policy that I mentioned in my original post. I've checked both cards on a non-work system and verified that BOOT.bin was the only file, and that the file size matched what had been generated by the Xilinx tools. With respect to adding a delay, would that be at the start of the main function in the FSBL? Thank you for the help.
  10. Good morning @jpeyron, Thank you for the follow-up. I'm seeing the exact same result with your project as I did with mine. I've put together a more detailed description of my setup and the steps I've been following: PC running SDK and Tera Term <------ USB/UART ------> CORA <------ SDIO -------> micro SD card Launch SDK Power CORA board Connect Tera Term to COM4 @ 115200baud Launch SDIO_write_file application (modified from xilffs_polled_example in xilffs_v3_6 library) from the SDK When prompted in Tera Term, send BOOT.bin file Power
  11. After some more digging, I'm still not there, but have an update that may help narrow down what's happening. The Xilinx AR# 59476 suggests: Please provide the status of INIT_B (high or low or blinking), REBOOT_STATUS and BOOT_MODE registers after the boot failure. REBOOT_STATUS is reading a value of 0x0040_0000 after POR, and reads 0x0060_0000 after I press the SRST button. The BOOT_MODE register reads 0x0000_0000 following a POR with the JP2 jumper removed. After a POR with JP2 installed, BOOT_MODE reads 0x0000_0005. These match my expectations based on studying the UG585 Z
  12. Hi Jon, It appears I do not have a successful boot from the SD card, even for just a UART helloworld. When I go through Run As -> Run Configurations from the SDK, the applications work as I expect. I'm trying to run on a CORA Z7 10 version with the XC7Z010-1CLG400, developing with Vivado and SDK 17.2. Looking at the Zedboard programming guide, I noticed a difference between what it describes in Appendix A and what I had been doing. It calls out including the HW.bit file in addition to the FSBL.elf and APPLICATION.elf files. Because my application only uses the Processor Subsy
  13. I am trying to boot a standalone application from a micro SD card on the CORA Z7 board. I'm working with a rather unconventional setup. Due to IT policy at work, the only micro SD card interface I have available is the one on the CORA board. Yesterday, I modified the example program that comes with the xilffs_v3_6 library to write and read back from an SD card. Then, I generated a BOOT.BIN file via Xilinx SDK -> Create Boot Image, using an auto-generated FSBL application and an auto-generated helloworld application. I wrote the BOOT.BIN to the SD card, but the CORA board did not seem t