MVS

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  1. MVS

    Discrete Fourier Transform V4.0

    A lot of thanks Dan. Im going to take a look at your module.
  2. MVS

    Discrete Fourier Transform V4.0

    Yes I am, Sr. Dan. The reset signal is SCLR (Synchronous Clear). This page is from IP core product guide. I leave here my .vhd and the testbench file. (Y) control.vhd TB.vhd
  3. MVS

    Discrete Fourier Transform V4.0

    Hello jpeyron, I made my design based on whats exposed in the first link. Compare this two images. I dont understand why, even if I enter zeroed vectors, i dont have a valid output; being the Fourier transform a sum, if the imput values are zeros, the outcomes should be zeros too... Thanks for your attention.
  4. Hello there, im working on a image encryption system and I want to implement the DFT ip core module from Xilinx. Here the results of the implementation.... I dont realize why the output data is XX if im entering the correct 2´s complement imput data... If someone has implemented this module before, I would appreciate some advice. control.vhd
  5. MVS

    Arty Z7-20 Serial Com

    Hello everyone, I bought an Arty z7-20 board a month ago and my first project depends on serial communication. I made a program in VHDL but I could not know which are the pins that I should assign to the uart. From schematic file, i understand that i have to comunicate the fpga with the pins C5 and C8, for Tx and Rx, on the chip bank500, but.... i dont see what are the pins to enable uart in the .xdc master file to do this. A lot of thanks for share your experience! I leave here a simple design to taste the uart. The idea is that the fpga recive a data and send it back to a terminal. SERIAL_ENSAYO.vhd