Paul Chang

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  1. Dear Sir, We used Vivado to generate a bitstream and download it to NetFPGA1G-CML. The top module contain 9 fully pipelined small circuits connected in series, then IN/OUTPUTs are connected to the PMOD. First of all, we opened each circuits separately and worked normally (about 21W or so). Later, when the two circuits were turned on, it was found that it did not work normally (about 25W).After restarting, each circuits was tested separately and it was still operating normally, so design seem no problem. Ideally, 9 small circuits should operate at the same time, But when we tested it, two small circuits would make the FPGA not work properly. Our architecture, using 12V power supply: We will observe the power supply by adding a wattage measuring machine. We measure coreV (schematic of this board). Then use an oscilloscope to observe the voltage across the capacitor in parallel with coreV. We found that the fpga core voltage dropped sharply, causing the internal function to fail to operate normally (the original 1V dropped to 0.6V) The wattage was about 24W at that time. Is such an IR drop too big?Do you know how to solve this issue? Our XDC file: set_property PACKAGE_PIN AA3 [get_ports clk_250_p] set_property PACKAGE_PIN AA2 [get_ports clk_250_n] set_property PACKAGE_PIN E23 [get_ports BBB_SCKO] set_property PACKAGE_PIN D19 [get_ports BBB_SCKI] set_property PACKAGE_PIN D25 [get_ports BBB_SDI] set_property PACKAGE_PIN F23 [get_ports BBB_SDO] set_property PACKAGE_PIN AA8 [get_ports RST_N] set_property IOSTANDARD LVCMOS33 [get_ports BBB_SCKI] set_property IOSTANDARD LVCMOS33 [get_ports BBB_SCKO] set_property IOSTANDARD LVCMOS33 [get_ports BBB_SDI] set_property IOSTANDARD LVCMOS33 [get_ports BBB_SDO] set_property IOSTANDARD LVDS [get_ports clk_250_p] set_property IOSTANDARD LVDS [get_ports clk_250_n] set_property IOSTANDARD LVCMOS18 [get_ports RST_N] Best Regards, Paul
  2. Hi @zygot We know the root cause, Thanks for your answer. Best Regards, Paul
  3. Dear Sir, I have a question about io voltage test. Our Configuration : NEXYS Video board + Xilinx FMC XM105 debug board. We set up IO to 1.2V , IO add a pull-up to 3.3V IO is set to output and logic 1 => voltage at this point: 1.2V =>OK IO is set to output and logic 0 => voltage at this point: 0V => OK IO is set to High-Z => The voltage at this point is about 2V IO is set to input => the voltage at this point is about 2V => Are them correct? Best Regards, Paul
  4. Dear Sir, We have two zedboard (One version is 2012 and another is 2019) When I run the ZedBoard FMC Pcam Adapter One to Four Camera Demo example. Old version board is no problem and new version board can not work.(Uart does not print anything and sometimes can not access ddr and ip address) It is currently suspected whether it is caused by the difference in DDR. (2012 zedboard's DDR) (2019 zedboard's DDR) We have tested the OOB demo from website and bundled SD card. Website's image seem fail. Bundled SD card is ok. (see attach log file) What's different between two version of zedboard? How to solve this issue? Best Regards, Paul log.txt
  5. Hi @artvvb, I have re-download and re-install the Vivado 2019.1. It can work now. Best Regards, Paul
  6. Dear Sir, I am test 1Mhz sinewave loop-back .(see attach file sig.png and spectrum.png and scope.png) And output the result to csv file. I try to analysis csv data in matlab. But the matlab spectrum result is different with result of waveforms.(matlab_spectrum.png) How to solve this? Best Regards, Paul fftscope.m test.csv
  7. Thanks for your help.
  8. Dear Sir, Is it possible to change RS485 to RS422 interface? How to set it to RS422 full duplex? Thank you. Best Regards, Paul
  9. Hi Arthur, I have tested this flow in vmware .(Ubuntu 18.04) It still can not work fine. Your project can not synthesis also. Ubuntu 18.04 Windows 10 Best Regards, Paul
  10. Hi Cristian , Thanks for your support. I don't know why I can not success to create the vivado project. Please see my process: 1. git clone --recursive https://github.com/Digilent/Eclypse-Z7-HW.git -b zmod_adc_dac/master 2. open vivado 2019.1 3. type below command in tcl window 4. The error is same. Best Regards, Paul
  11. Hi Cristian, I am using Windows 10. Is it only support Linux os? Best Regards Paul
  12. Dear Sir, I would like to re-create the zmod_adc_dac vivado project. I have follow this link But it seems can not recreate the Vivado project. Error below: (more info and please see log.txt) can't read "assoc": no such variable ERROR: [BD 41-1273] Error running post_config_ip TCL procedure: can't read "assoc": no such variable update_assoc_busif Line 6 Best Regards, Paul log.txt
  13. Dear sir, I would like to know Analog Outputs limitation. Does it can support the requirement ? AC Freq range 0.05 Hz~120Hz AC voltage range: -10mV ~ +10mV AC resolution : <0.1mV DC offset is greater than -1000mV ~ +1000mV: DC offset resolution 5mV special AC AC overload test : 1 Vpp @50Hz/60Hz Another question: Can it measure input loop current <0.1uA? Best Regards Paul
  14. Dear Sir, I took my NB and tried to read the JTAG-SMT2-NC module via USB, but I always had the error "usb device descriptor failure code" Is there any way to solve this problem? Best Regards Paul