Paul Chang

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  1. hi @zygot Because I want both board can receive the trigger signal at the same time. That's why I set up this simple circuit. Thanks for your suggestion. AHC244 seem a good solution. Best Regards Paul
  2. Hi @JColvin, My two boards will wait this trigger input and both send the data at the same time. external trigger circuit (Two boards's PMOD GND ,I think it does not need two board's vcc ,right?) I think I can use the pmondbtn . It seems more better. Can I use it to trigger two boards? My top level file: (It is not xilinx IP) module top1( input clk, //125Mhz input rst, input trigger, //external trigger output reg [3:0]led, output reg z //output s
  3. Dear Sir, I would like to use a external trigger circuit which it can trigger two boards. (PMOD as input) When I program fpga bit to my board and measure its PMOD input. The PMOD input is 3.3v. I am not sure it is correct or not. How to set up the input as low ? set_property PULLDOWN true [get_ports trigger_0] or PUDC_B external trigger circuit (Two boards's VCC and GND) my xdc file (PYNQ z1) ## Pmod Header JA set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33} [get_ports trigger] Best Regards Paul
  4. Hi @attila Thanks for your support. 1. Do you have its jitter spec? 2.Could you tell me what's the driver circuit? Does it mean more current? Because the nyquist theorem then the external clock is better in 10Mhz~30Mhz. Best Regards Paul
  5. Dear Sir, 1.Do you have arbitrary waveform generator's harmonic and phase noise spec ?(Are you using sine wave for measurement?) 2.If Logic Analyzer uses state mode(external clock), what is its maximum state clock rate? Best Regards Paul
  6. @cristian.Fatu After our test , the FPGA's operating wattage cannot be too high. Thanks for your help.
  7. @zygot Thanks for your answer.
  8. Dear Sir, I have some zmod ADC demo questions blow: 1.About USB104A7 ZmodADC Demo: This demo has length of command . What's the maximum length? Can I save a large data size? 2.I have checked the code below: The TRANSFER_LEN is 0x400 . Can I setup it and save the a large data size? Best Regards, Paul
  9. hi Cristian, Any update information? Your comments and suggestions are welcome! Best Regards Paul
  10. Dear Sir, We used Vivado to generate a bitstream and download it to NetFPGA1G-CML. The top module contain 9 fully pipelined small circuits connected in series, then IN/OUTPUTs are connected to the PMOD. First of all, we opened each circuits separately and worked normally (about 21W or so). Later, when the two circuits were turned on, it was found that it did not work normally (about 25W).After restarting, each circuits was tested separately and it was still operating normally, so design seem no problem. Ideally, 9 small circuits should operate at the same time, But when we tested it,
  11. Hi @zygot We know the root cause, Thanks for your answer. Best Regards, Paul
  12. Dear Sir, I have a question about io voltage test. Our Configuration : NEXYS Video board + Xilinx FMC XM105 debug board. We set up IO to 1.2V , IO add a pull-up to 3.3V IO is set to output and logic 1 => voltage at this point: 1.2V =>OK IO is set to output and logic 0 => voltage at this point: 0V => OK IO is set to High-Z => The voltage at this point is about 2V IO is set to input => the voltage at this point is about 2V => Are them correct? Best Regards, Paul
  13. Dear Sir, We have two zedboard (One version is 2012 and another is 2019) When I run the ZedBoard FMC Pcam Adapter One to Four Camera Demo example. Old version board is no problem and new version board can not work.(Uart does not print anything and sometimes can not access ddr and ip address) It is currently suspected whether it is caused by the difference in DDR. (2012 zedboard's DDR) (2019 zedboard's DDR) We have tested the OOB demo from website and bundled SD card. Website's image seem fail. Bundled SD card is ok. (see attach log
  14. Hi @artvvb, I have re-download and re-install the Vivado 2019.1. It can work now. Best Regards, Paul