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  1. Hi, The design of HDMI using GT takes a little time. I decided to lower fps to 30 first. I tried it with a simple HDMI design to isolate the problem. But the result did not change. I think that fps has fallen and timing problems are gone. But the screen got stained red. Is there anything wrong with my setting? Thank you. ―――――――――――――――――――――――――――――――――――――――――――――――――― ## Clock Signal set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports sys_clock] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clock] ## HDMI in set_property -dict {PACKAGE_PIN W4 IOSTANDARD TMDS_33} [get_ports hdmi_rx_clk_n] set_property -dict {PACKAGE_PIN V4 IOSTANDARD TMDS_33} [get_ports hdmi_rx_clk_p] set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_hpa] set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports hdmi_rx_ddc_scl_io] set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS33} [get_ports hdmi_rx_ddc_sda_io] set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports hdmi_rx_txen] set_property -dict {PACKAGE_PIN AA3 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_n[0]}] set_property -dict {PACKAGE_PIN Y3 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_p[0]}] set_property -dict {PACKAGE_PIN Y2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_n[1]}] set_property -dict {PACKAGE_PIN W2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_p[1]}] set_property -dict {PACKAGE_PIN V2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_n[2]}] set_property -dict {PACKAGE_PIN U2 IOSTANDARD TMDS_33} [get_ports {hdmi_rx_data_p[2]}] ## HDMI out set_property -dict {PACKAGE_PIN U1 IOSTANDARD TMDS_33} [get_ports hdmi_tx_clk_n] set_property -dict {PACKAGE_PIN T1 IOSTANDARD TMDS_33} [get_ports hdmi_tx_clk_p] set_property -dict {PACKAGE_PIN Y1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_n[0]}] set_property -dict {PACKAGE_PIN W1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_p[0]}] set_property -dict {PACKAGE_PIN AB1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_n[1]}] set_property -dict {PACKAGE_PIN AA1 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_p[1]}] set_property -dict {PACKAGE_PIN AB2 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_n[2]}] set_property -dict {PACKAGE_PIN AB3 IOSTANDARD TMDS_33} [get_ports {hdmi_tx_data_p[2]}] ## HDMI clock create_clock -period 13.468 [get_ports hdmi_rx_clk_p] create_clock -period 13.468 [get_ports TMDS_Clk_p] create_clock -period 13.468 [get_ports PixelClk] ――――――――――――――――――――――――――――――――――――――――――――――――――
  2. Hi, jpeyron Thank you for the information. I will do my best referring to it. Thank you.
  3. Hi, jdajul Thank you for your reply. I tried inserting and removing HDMI, but there was no change .... Apparently the pattern will change every time you build. It is really puzzling.
  4. Hi, jpeyron Thank you for your reply. This HDMI design was designed using dvi2rgb (1.9), rgb2dvi (1.4), ClockingWizard (6.0) with reference to Nexys Video User Demo. I also contacted AVNET x-hotline. The answer is, 「1920 x 1080 The pixel clock (148.5 MHz) operation of 60 p requires 742.5 MHz for IO, but the upper limit of BUFIO of Artix chip is 680 MHz. Since it exceeds the upper limit, 1920 x 1080 60p can not be guaranteed because there are things that do not work and those that work depending on individual differences and environments in operation. If you drop fps to 30 or design it with HDMI using GT, it will solve it.」 I would like to try HDMI design using GT. Are dvi 2 rgb and rgb 2 dvi correct on HDMI IP using IO? Also, do you have digient for HDMI IP that uses GT? Thank you.
  5. Hello, @ jpeyron Thank you for your reply. Thank you for investigating! I am sorry, I can not describe the detail of image processing .... It inputs images, performs arithmetic processing on all pixels, and outputs images in real time. And occupies much of the FPGA resources. However, this phenomenon also occurs on the function of HDMI passthrough. it's incomprehensible. I think I will investigate cable connection and whether there is a place inside the project that is bad. Thank you.
  6. Please forgive immature English Hello I am developing a project of image processing on the NexysVideo board And it is completed and it works well at 1920 x 1080 p 60 Hz Recently I bought a new NexysVideo board And I programmed the same project but there is a problem with the operation ※ "Symptoms similar to" Defective pixel "and" Moire "appear (see attached image) I have a question Are there any specifications differences between NexysVideo board specifications this spring (2018/04) and the latest (2018/11)? Or is it exactly the same? Thank you
  7. Hi @JColvin Thank you for your reply. Ok, I understand. I will question the Xilinx Forum. thank you everyone.
  8. Hi @BogdanVanca, Thank you for your reply. I'm glad. I am also puzzled for the first time to work with the e - FUSE register. When register setting of e-FUSE was done, it was not possible to find the register named "FUSE_SEC". I refer to the document (UG908), perhaps "FUSE_SEC" may be a register that can be controlled only by UltraScale or UltraScale + devices? In setting e-FUSE, the USER bit was left blank. The values are as follows. -------------------------------------------------------------------- ---------- [7: 0] FF [31: 8] FF_FFFF -------------------------------------------------------------------- ---------- Also, the FUSE_CNTL register is set as follows. -------------------------------------------------------------------- ---------- CFG_AES_Only 1 (Forces use of AES key stored in device) AES_Exclusive 1 (Disable partial reconfiguration) W_EN_B_Key_User 1 (Disables programming of AES key and of USER register) R_EN_B_Key 1 (Disables reading of AES key) R_EN_B_User 1 (Disables reading of user code) -------------------------------------------------------------------- ---------- We set all the above FUSE_CNTL registers from 0 to 1. Until this e-FUSE setting was done, because programming to QSPI was possible I may be the cause of this setting being unable to program in QSPI. (If you disable reading AES key, you can not program to QSPI ...?)
  9. Hello. I am a beginner in FPGA. Also I am poor in English. Sorry. I am developing with Nexys Video. Although the design is complete, I am suffering from using QSPI Config and e-FUSE security together. I tried QSPI Config first. This worked well. Next I tried e-FUSE security. I wrote the security key and finished setting the FUSE register, After that, I could not program the QSPI. When executing the program, the following error will be displayed and will be aborted. -------------------------------------------------------------------- [Labtools 27-3165] End of startup status: LOW -------------------------------------------------------------------- You can not configure from QSPI, but you can configure an encrypted bit / bin file using JTAG. I replaced the USB cable with reference to the past forum, but there was no effect .... What does this error mean? Is there a solution for using QSPI Config and e-FUSE security together? Please tell me if you need information to solve the problem. Thank you koseki.