Joseph Fourier

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Joseph Fourier last won the day on August 28 2018

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  1. I try to estimate how much bytes I can pump through the SoC on Arty Z7-20 at max speed. Based on ug585 and Arty Z7 Reference, I find following max throughputs: 1) Ethernet <---> Zynq PS: 125 MB/sec 2) USB <---> Zynq PS: 60 MB/sec 3) SD <---> Zynq PS: 25 MB/sec 4) DDR <---> Zynq PS: 2100 MB/sec (16 bit data bus; 1050 Mbit per lane) Inside SoC: 1) Zynq on chip memory <---> Zynq PL: 1200 MB/sec READ + 1200 MB/sec WRITE (AXI_HP3) 2) Zynq PS <---> Zynq PL: 1200 MB/sec READ + 1200 MB/sec WRITE (AXI_GP0 and AXI_GP1 combined) 3) Zynq DDR controller <---> Zynq PL: 1200 MB/sec READ + 1200 MB/sec WRITE (AXI_HP0) =============== 1) Is my analysis correct? 2) If yes, it looks like the fastest channel to external world is Ethernet, if input data is several Gigabytes? 3) I was thinking to attach an external USB SSD to use as input data to PS+PL, but actual 60 MB/sec bandwidth will be probably much lower?
  2. @hamster I was able to run your AXI Slave interface. It works great! It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it). I have some questions about your AXI Slave design: 1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type? 2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work? 3) Where WRAP type is necessary? How to use PS to work in WRAP mode? You may also update your wiki page with following: 0) Create provided VHDL files 1) Create a block-diagram and add PS IP core to it 2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.) 3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO 4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports 5) Generate VHDL wrapping code for this block diagram 6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version) 7) This will auto-connect block-diagram external ports with axi_test_top 8 ) Add constrains file and rename/uncomment external ports where necessary 9) Generate bitstream 10) File->Export->Hardware and create .hwf file which contains PS configuration 11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project 12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc. 13) Add hello_world.c application to the project @hamster Thank you very much. I've learned a bunch of new things thanks to your help!
  3. >> That is based on the address window assigned to the AXI port in the PS configuration. In that case for a completely open description there must be an additional source file where this information is presented, no?
  4. Your simple AXI slave looks very interesting, thanks! What I still don't understand: 1) how do you get this number: (uint32_t *)(0x43C0<<16) is it a kind of memory-mapped AXI register in PS address space? but I cannot find it in documentation 2) is your hello.c program a standalone code (will run not under Linux), right? It would be helpful to see a Makefile or just commands how to build an image from C code. Thanks for your great help!
  5. For PS to write to BRAM, PL must contain an AXI logic configured, right? Otherwise I cannot see other data channels on the Zynq diagram
  6. I have got Arty Z7-20 with hope to design a special purpose hardware with only open description (no proprietary IPs, pure VHDL+Constrains). Now, after a week of intensive Google search I am still completely out of any viable option. I have read Zynq Tech Reference and while it describes the SoC architecture, it doesn't provide any HDL example of how to copy data between PL and PS. If there are no AXI signals available on HDL behav level, can data be transferred alternatively maybe directly through DDR or anything else? PS: I surely understand I need to design AXI controller in HDL, but this is what I want to do. Thanks!