Run Yu

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  1. Like
    Run Yu got a reaction from Haris in Help With A Zybo Video Design   
    Hi Marshall,
    Thank you for your response. I finally figured out that I only need one XDC file for mapping ports instead of including all of those XDC files at the same time, since dvi2rgb core's XDC files will be applied during synthesis. The reason why I need to change dvi2rgb.xdc and dvi2rgb_occ.xdc is because Zybo has a maximum buffer bit clock of 600MHz but those xdc files constrain TMDS_Clk at 165MHz which requires 825MHz buffer bit clock. On the user guide it recommands to constrain TMDS_Clk at 1/5 of the maximum bit clock, which results in 600MHz / 5 = 120MHz pixel clock constraint. Also, 200MHz reference clock is required by the core so I use the clock wizard to feed that 200MHz. 
    One thing I am not sure is how that 75MHz should be created? I set up the constraint "create_clock -period 13.334 [get_ports TMDS_Clk_p]" and use report_clock_network tcl command to check. It reported that TMDS_Clk_p = 75MHz but when I probed to the TMDS_Clk_p pin, it was logic forever. I also probed the generated pixel clock but it was garbage. So I am not sure does "create_clock -period 13.334 [get_ports TMDS_Clk_p]" means generating a 75MHz clock at TMDS_Clk_p or just setting up the upper limit. 
    Here is the link to dvi2rgb core I mention above, you might be able to take a look into it and help me out if you have time. https://github.com/DigilentInc/vivado-library/tree/master/ip/dvi2rgb_v1_4
    For "VDD" and "GND" connection, I mean tie to either logic 1 or 0 instead of physical pins.
     
    Here is the link to the demo folder but as Chris mentioned, it is built in EDK instead of Vivado and I am not using the cores used by this demo. Check it out if you are interested.
    https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo
    Any help/thought/suggestion would be very welcome and thank you so much for you time of replying my questions!
     
    Run
  2. Like
    Run Yu reacted to lijieming in Help With A Zybo Video Design   
    Dear Chris,
    1. Like Run suggested, the error "IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  BiDi RangeId: 1 Drv: 12  has only 0 sites available on device, but needs 2 sites."  such kind of problem is caused by one or more unconnected external ports on your block diagram. Please check your diagram first to make sure all unused external ports are deleted. (this problem will occur on both  2014.4 and 2015.1)
    2. For the DDC part, the HDMI protocol described it clearly that this is a mechanism to let video transmitter and receiver to communicate which each other. By exchanging information, the transmitter could know the detail configuration(ability) of the receiver part (what resolution, frame rate, format of signal the receiver can process). This is a necessary part in HDMI transmission and can not be ignored or deleted.
    3. Currently the problem you encountered is how to synthesis the Bi-Directional inner control ports into a signal Bi-Di external port. To solve this problem, first you should understand what is a bi-di port and its mechanism(I am sure you know it). Secondly, in Xilinx ISE, three bi-di control ports can be easily synthesized together by adding a constrain command in the .ucf file. In vivado the goal can't be achieved by only modify the .xdc. In my way, i directly modified the DVI2RGB ip core, the top_module i mentioned is the top module of the ip core (the dvi2rgb.vhd file). The core is written by VHDL, modify the following:
    a. In the port description change DDC ports to below
     -- Optional DDC port
          DDC_SDA : inout std_logic;
          DDC_SCL : in std_logic;
    b. add HPD and CEC port in the end of port def
          HDMI_HPD : out std_logic;
          HDMI_OUT_EN : out std_logic
    c.  in the behavioral part add signal def and logic
    architecture Behavioral of dvi2rgb is
    .......
    signal hpd : std_logic;
    .......
    begin
    DDC_SCL_I <= DDC_SCL;
    DDC_SDA <= DDC_SDA_O when DDC_SDA_T = '0' else 'Z';
        DDC_SDA_I <= DDC_SDA;
        
    HDMI_OUT_EN <= '0';
    HDMI_HPD <= hpd;
    .......
    d. in the TMDS_ClockingX call add port "hpd"
    TMDS_ClockingX: entity work.TMDS_Clocking
       generic map (
          kClkRange => kClkRange)
       port map (
    .........
    hpd => hpd
       );
    f. in the TMDS_ClockingX module(vhd file) add "hpd" def. this will active the HDMI transmittion only after the sink core has been locked
    entity TMDS_Clocking is
       Generic (
          kClkRange : natural := 1);  -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5
       Port (
          .........
          hpd : out std_logic);
    end TMDS_Clocking;
    architecture Behavioral of TMDS_Clocking is
    ..........
    begin
    hpd <= aDlyLckd;
    .........
    the above is all you need to make this core compatible with HDMI. after modification -> save -> repackage ip core
    4. All you need in your project xdc file is really sample if modification has been done inside ip core. below is my xdc
    set_property PACKAGE_PIN H16 [get_ports HDMI_CLK_P]
    set_property PACKAGE_PIN H17 [get_ports HDMI_CLK_N]
    set_property PACKAGE_PIN D19 [get_ports {HDMI_D_P[0]}]
    set_property PACKAGE_PIN C20 [get_ports {HDMI_D_P[1]}]
    set_property PACKAGE_PIN B19 [get_ports {HDMI_D_P[2]}]
    set_property PACKAGE_PIN D20 [get_ports {HDMI_D_N[0]}]
    set_property PACKAGE_PIN B20 [get_ports {HDMI_D_N[1]}]
    set_property PACKAGE_PIN A20 [get_ports {HDMI_D_N[2]}]
    set_property IOSTANDARD TMDS_33 [get_ports HDMI_CLK_*]
    set_property IOSTANDARD TMDS_33 [get_ports HDMI_D*]
    set_property PACKAGE_PIN G17 [get_ports HDMI_SCL]
    set_property PACKAGE_PIN G18 [get_ports HDMI_SDA]
    set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SCL]
    set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SDA]
    set_property PACKAGE_PIN E18 [get_ports HDMI_HPD]
    set_property IOSTANDARD LVCMOS33 [get_ports HDMI_HPD]
    set_property PACKAGE_PIN F17 [get_ports HDMI_OUT_EN]
    set_property IOSTANDARD LVCMOS33 [get_ports HDMI_OUT_EN]
    create_clock -name sysclk -period 25 -waveform {0 12.5} [get_ports HDMI_CLK_P]
    this is all you need for your project.
     
    Jieming
  3. Like
    Run Yu got a reaction from digicloud14 in Help With A Zybo Video Design   
    Hey Chris,
    You could disable DDC feature by opt out that option when you customize the IP.
     
    Run
  4. Like
    Run Yu reacted to lijieming in Help With A Zybo Video Design   
    Hey Guys,
    Glad to see your progress of the video project. Sorry for coming back late (have been on vacation aboard last week). Still willing to help with anything
    Jieming
  5. Like
    Run Yu reacted to mwingerson in Help With A Zybo Video Design   
    Glad I could help.
    Marshall
  6. Like
    Run Yu reacted to digicloud14 in Help With A Zybo Video Design   
    Well, Run looks like you've got all the help you need from Marshall! You can also check out this other thread I started here https://forum.digilentinc.com/topic/286-hdmi-sink-on-zybo-zynq/ where Sam has been helping me with the design I mentioned in the initial post as he has been working on a similar design as well.
  7. Like
    Run Yu reacted to mwingerson in Help With A Zybo Video Design   
    Hey guy,
    I got it working with a little help from Sam.
    To simplify the whole thing, I trimmed out all of the zynq associated blocks since this is project isn't using the PS and removed the extra XDCs.  
    The DDC channels on the dvi2rgb core need to assigned correctly and it is a bit of a pain.  
    Delete all connections right-click DDC  Select "make external"  open the design wrapper and there should be two signals names "ddc_scl_io" and "ddc_sda_io" modify the Zybo master XDC to reflect those names in the HDMI group.
    Sam helped me fix the timing errors associated with timing.  The fix was to comment out comment out this the create_clock line in "dvi2rgb.xdc".  The new file should look like this:
    The issue is that the "create_clock" command is forcing the TMDS_Clk_p to be a frequency that cannot be supported by FPGA on the Zybo causing the timing error.  Removing it allows the solution in the TMDS clock generate work.
    Finally, change the clocking wizard block to be in the PLL instead of the MMCM.  The dvi2rgb core uses an MMCM and the clocking wizard wants to use a MMCM but there is only one MMCM in that section of the FPGA so tell the clocking wizard to use a PLL.

    I uploaded working directory to my github: here
    Hope this helps!
    Marshall
  8. Like
    Run Yu got a reaction from digicloud14 in Help With A Zybo Video Design   
    Hey Chris,
    I believe you'd better name your port the way dvi2rgb uses which like you mentioned, TMDS_Data_n[2:0], TMDS_Data_p[2:0], TMDS_Clk_p, and TMDS_Clk_n. Otherwise you have to match those names to what you use on the block diagram and of course the names on zybo's port xdc file. So I did the same way you did, name all TMDS ports on block diagram TMDS_Data_n[2:0], TMDS_Data_p[2:0], TMDS_Clk_p, and TMDS_Clk_n. 
    That warning comes out because you manually map the TMDS connections to Zybo's ports while the core set them up as an interface connection but that should be OK (not 100% sure). I did the same way while using rgb2dvi, manually map them to Zybo's HDMI connector instead of using interface but still works. 
    And I will try to remove the logic tied to HDMI_OUT_EN and see if anything happen. I plan to use another Zybo with HDMI source (rgb2dvi) with output clock and data running forever, to drive another Zybo with HDMI sink (dvi2rgb) and see what would happen. But I don't have another Zybo at this moment. I will update as soon as I have chane to do this.
    Keep up Chris, hope you are also getting some progressive outcomes. I have spent too long on this and other classmates are also stuck. It is a part of my class's final project but not sure if I could get it before the end of this quarter.
    Anyway, good luck!
    Run
  9. Like
    Run Yu reacted to digicloud14 in Help With A Zybo Video Design   
    Run,

    Sam from Digilent mentioned in another post that HDMI_OUT_EN needs to be driven low in order for it to act as a sink. That determines whether the 5V and HPD act as inputs or outputs, so if I'm understanding correctly there is no need for you to manually tie those high or low. I'm not 100% sure however, so if anyone else knows please correct me.

    Also, Run, did you run into a problem such as this while making sure that the DVI2RGB port connections matched those in the XDC file:
    WARNING: [BD 41-1306] The connection to interface pin /dvi2rgb_0/TMDS_Data_n is being overridden by the user. This pin will not be connected as a part of interface connection TMDS
    I opened the XDC file to find the names of the ports, and created ports in the block diagram that matched those. When I connected the ports I just created to the pins of the DVI2RBG core, i received the above warning. Have I done something wrong or is this expected?
     
    *Just realized I may have been looking at the wrong XDC file. Run, do you know what the proper names for the ports from the DVI2RGB core XDC are? Are they TMDS_Data_n[2:0], TMDS_Data_p[2:0], TMDS_Clk_p, and TMDS_Clk_n?
  10. Like
    Run Yu got a reaction from digicloud14 in Help With A Zybo Video Design   
    Hi Marshall,
    Thank you for your response. I finally figured out that I only need one XDC file for mapping ports instead of including all of those XDC files at the same time, since dvi2rgb core's XDC files will be applied during synthesis. The reason why I need to change dvi2rgb.xdc and dvi2rgb_occ.xdc is because Zybo has a maximum buffer bit clock of 600MHz but those xdc files constrain TMDS_Clk at 165MHz which requires 825MHz buffer bit clock. On the user guide it recommands to constrain TMDS_Clk at 1/5 of the maximum bit clock, which results in 600MHz / 5 = 120MHz pixel clock constraint. Also, 200MHz reference clock is required by the core so I use the clock wizard to feed that 200MHz. 
    One thing I am not sure is how that 75MHz should be created? I set up the constraint "create_clock -period 13.334 [get_ports TMDS_Clk_p]" and use report_clock_network tcl command to check. It reported that TMDS_Clk_p = 75MHz but when I probed to the TMDS_Clk_p pin, it was logic forever. I also probed the generated pixel clock but it was garbage. So I am not sure does "create_clock -period 13.334 [get_ports TMDS_Clk_p]" means generating a 75MHz clock at TMDS_Clk_p or just setting up the upper limit. 
    Here is the link to dvi2rgb core I mention above, you might be able to take a look into it and help me out if you have time. https://github.com/DigilentInc/vivado-library/tree/master/ip/dvi2rgb_v1_4
    For "VDD" and "GND" connection, I mean tie to either logic 1 or 0 instead of physical pins.
     
    Here is the link to the demo folder but as Chris mentioned, it is built in EDK instead of Vivado and I am not using the cores used by this demo. Check it out if you are interested.
    https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo
    Any help/thought/suggestion would be very welcome and thank you so much for you time of replying my questions!
     
    Run
  11. Like
    Run Yu reacted to mwingerson in Help With A Zybo Video Design   
    Hey Run,
    Where did you get the demo?  I would like to see what you are working from.
    1.  I suspect you just need to change the clocking wizard that feed the dvi2rgb core to 75MHz instead of 200MHz but I cannot be sure without poking around a little.
    Although, I have only ever used one ucf/xdc file per design so I am wondering if you are having issues with that.  I could see how using multiple files could work but I don't have any experience with it.  
    As for your errors, "[Common 17-55] 'set_property' expects at least one object. " error is caused by a mismatch between the defined port in Vivado and the xdc.  In this case, I would get rid of the "dvi2rgb.xdc" and the "dvi2rgb_ooc.xdc" files and rely on the zybo master xdc.  
    Then I would change the zybo xdc to match the port names that are attached to the dvi2rgb core.  
    2. I'll ask around but I think you should have one universal XDC.
    3. Make sure to change the XDC to reflect the port names you used.
    4. Do you mean you tied them by outputting them to a pin and using a wire to put them to VDD or GND?  That isn't a good idea.  Those pins are being driven as outputs and driving them to VDD or GND could short them and damage the pins.  On inputs that would be fine but I like to tie the signals to a switch or button.  On outputs, leave them unconnected.
    Hope this helps.
    Marshall
     
     
  12. Like
    Run Yu reacted to digicloud14 in Help With A Zybo Video Design   
    Hey Run,

    The GoPro Project found here https://github.com/LariSan/Digilent-Maker/tree/master/Zybo/zybo_video_demo does exactly what you're trying to do. It takes in HDMI input and forwards it to the VGA for display. Instead of the DVI2RBG Core, it uses the HDMI_RX Core mentioned above, but they are almost identical. The project is in EDK however, and not Vivado, but a look at the source files could possibly answer some of your questions. I'm not exactly sure about the timing constraints, but Jieming above seems to suggest that in his design the timing constraints failed but the video still displayed anyway. Sorry I can't help you more, I'm in a similar position, still trying to figure everything out! Best of luck, come back and update here if you figure it out, I'd love to see the results. And I'll do the same.

    Regards,
    Chris
  13. Like
    Run Yu got a reaction from digicloud14 in Help With A Zybo Video Design   
    Hey guys,
    I am working on a same kind of project, trying to use the dvi2rgb ip mentioned. I am trying to get input from the HDMI port and display that through the VGA. I am pretty new to Zybo/Vivado 2014.4 and HDMI stuff so I come up with the following questions:
    1. I am trying to set the output to be 720p which means I need a ~75MHz pixel clock from the dvi2rgb ip and the Refclk is set to 200MHz. Does it mean that I need to constrain the TMDS clock to 75MHz on the dvi2rgb.xdc & dvi2rgb_ooc.xdc files? I did the calculation and comes up with a change on the xdc file: "create_clock -period 13.334 [get_ports TMDS_Clk_p]". And actually I am not sure how to use those xdc files. Do I need to also include them to the "constraints" with the zybo board constraint? 
    I did so but it keeps giving me the following critical warnings:
    [Common 17-55] 'set_property' expects at least one object. [dvi2rgb.xdc":7]
    (line on xdc file: set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay])
     
    [Common 17-55] 'set_property' expects at least one object. [dvi2rgb.xdc":8]
    (line on xdc file: set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX])
     
    [Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_pins RefClk]'. [dvi2rgb_ooc.xdc":2]
    (line on xdc file: create_clock -period 5.000 [get_pins RefClk])
     
     
     
    2. If that's not the way to use the xdc files, what that should be?
    3. Also, do I need to do something special to the DDC_SCL_I and DDC_SDA_I? I basically just connect them to ports.
    4. Last I just tie HPD to VDD, and OUT_EN to GND. Is that OK?

    I could generate the bitstream file but as it is up the the zybo using Adept, not any signal comes out from the output of the dvi2rgb module (I mapped PixelClk, locked, HS and VS to the LEDs so I could probe the frequencies but all of them are low).
    Thank you very much for any help and suggestions!
     
    Run