Run Yu

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Posts posted by Run Yu

  1. Chris,

    You don't need to create additional clock for the TMDS_Clk_p or redo the "create_clock" constraint. The way that clock generate will be done by the HDMI source (I guess). Basically the HDMI source reads the edid file through I2C, finds what resolution Zybo supports (1280x1024 is the one detailed based on the dvi2rgb doc) and generates the correct clock frequency for data transmission. So you just need to have TMDS_Clk connects to the HDMI source (as TMDS_data[2]) and it will work out for you. On my case, the [email protected] resolution produces 108MHz pixel clock. If you have a scope, you could verify that clock frequency. It is the 4th pair of differential signal on the HDMI connector, from left to right.

    And yes, use PLL for clocking wizard.

    Hope this helps, I could share some of my works with you if you want. Just let me know.


  2. Hey Chirs,

    I encountered same sort of the problem you have everytime when I forgot to delete the unconnected port on diagram, but have been commented out the port map on xdc file. For example, leave iic_0_scl_io and iic_0_sda_io port float in the diagram, but comment them out on the xdc will trigger this error.



  3. Hey Marshall,

    Glad that you help us out, it works very well! Really appreciate! I kept changing the clock constraint on the xdc file but never be brave eoungh to remove that out.:rolleyes: Now I am able to catch up on my project.


  4. Hey Chris,

    I believe you'd better name your port the way dvi2rgb uses which like you mentioned, TMDS_Data_n[2:0], TMDS_Data_p[2:0], TMDS_Clk_p, and TMDS_Clk_n. Otherwise you have to match those names to what you use on the block diagram and of course the names on zybo's port xdc file. So I did the same way you did, name all TMDS ports on block diagram TMDS_Data_n[2:0], TMDS_Data_p[2:0], TMDS_Clk_p, and TMDS_Clk_n. 

    That warning comes out because you manually map the TMDS connections to Zybo's ports while the core set them up as an interface connection but that should be OK (not 100% sure). I did the same way while using rgb2dvi, manually map them to Zybo's HDMI connector instead of using interface but still works. 

    And I will try to remove the logic tied to HDMI_OUT_EN and see if anything happen. I plan to use another Zybo with HDMI source (rgb2dvi) with output clock and data running forever, to drive another Zybo with HDMI sink (dvi2rgb) and see what would happen. But I don't have another Zybo at this moment. I will update as soon as I have chane to do this.

    Keep up Chris, hope you are also getting some progressive outcomes. I have spent too long on this and other classmates are also stuck. It is a part of my class's final project but not sure if I could get it before the end of this quarter. :(

    Anyway, good luck!


  5. Hi Marshall,

    Thank you for your response. I finally figured out that I only need one XDC file for mapping ports instead of including all of those XDC files at the same time, since dvi2rgb core's XDC files will be applied during synthesis. The reason why I need to change dvi2rgb.xdc and dvi2rgb_occ.xdc is because Zybo has a maximum buffer bit clock of 600MHz but those xdc files constrain TMDS_Clk at 165MHz which requires 825MHz buffer bit clock. On the user guide it recommands to constrain TMDS_Clk at 1/5 of the maximum bit clock, which results in 600MHz / 5 = 120MHz pixel clock constraint. Also, 200MHz reference clock is required by the core so I use the clock wizard to feed that 200MHz. 

    One thing I am not sure is how that 75MHz should be created? I set up the constraint "create_clock -period 13.334 [get_ports TMDS_Clk_p]" and use report_clock_network tcl command to check. It reported that TMDS_Clk_p = 75MHz but when I probed to the TMDS_Clk_p pin, it was logic forever. I also probed the generated pixel clock but it was garbage. So I am not sure does "create_clock -period 13.334 [get_ports TMDS_Clk_p]" means generating a 75MHz clock at TMDS_Clk_p or just setting up the upper limit. 

    Here is the link to dvi2rgb core I mention above, you might be able to take a look into it and help me out if you have time.

    For "VDD" and "GND" connection, I mean tie to either logic 1 or 0 instead of physical pins. :)


    Here is the link to the demo folder but as Chris mentioned, it is built in EDK instead of Vivado and I am not using the cores used by this demo. Check it out if you are interested.

    Any help/thought/suggestion would be very welcome and thank you so much for you time of replying my questions!



  6. Hey guys,

    I am working on a same kind of project, trying to use the dvi2rgb ip mentioned. I am trying to get input from the HDMI port and display that through the VGA. I am pretty new to Zybo/Vivado 2014.4 and HDMI stuff so I come up with the following questions:

    1. I am trying to set the output to be 720p which means I need a ~75MHz pixel clock from the dvi2rgb ip and the Refclk is set to 200MHz. Does it mean that I need to constrain the TMDS clock to 75MHz on the dvi2rgb.xdc & dvi2rgb_ooc.xdc files? I did the calculation and comes up with a change on the xdc file: "create_clock -period 13.334 [get_ports TMDS_Clk_p]". And actually I am not sure how to use those xdc files. Do I need to also include them to the "constraints" with the zybo board constraint? 

    I did so but it keeps giving me the following critical warnings:

    [Common 17-55] 'set_property' expects at least one object. [dvi2rgb.xdc":7]

    (line on xdc file: set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells DataDecoders[*].DecoderX/InputSERDES_X/InputDelay])


    [Common 17-55] 'set_property' expects at least one object. [dvi2rgb.xdc":8]

    (line on xdc file: set_property IODELAY_GROUP dvi2rgb_iodelay_grp [get_cells TMDS_ClockingX/IDelayCtrlX])


    [Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_pins RefClk]'. [dvi2rgb_ooc.xdc":2]

    (line on xdc file: create_clock -period 5.000 [get_pins RefClk])




    2. If that's not the way to use the xdc files, what that should be?

    3. Also, do I need to do something special to the DDC_SCL_I and DDC_SDA_I? I basically just connect them to ports.

    4. Last I just tie HPD to VDD, and OUT_EN to GND. Is that OK?


    I could generate the bitstream file but as it is up the the zybo using Adept, not any signal comes out from the output of the dvi2rgb module (I mapped PixelClk, locked, HS and VS to the LEDs so I could probe the frequencies but all of them are low).

    Thank you very much for any help and suggestions!