Run Yu

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  1. Chris, You don't need to create additional clock for the TMDS_Clk_p or redo the "create_clock" constraint. The way that clock generate will be done by the HDMI source (I guess). Basically the HDMI source reads the edid file through I2C, finds what resolution Zybo supports (1280x1024 is the one detailed based on the dvi2rgb doc) and generates the correct clock frequency for data transmission. So you just need to have TMDS_Clk connects to the HDMI source (as TMDS_data[2]) and it will work out for you. On my case, the [email protected] resolution produces 108MHz pixel clock. If you have a scope, you
  2. Hey Chirs, I encountered same sort of the problem you have everytime when I forgot to delete the unconnected port on diagram, but have been commented out the port map on xdc file. For example, leave iic_0_scl_io and iic_0_sda_io port float in the diagram, but comment them out on the xdc will trigger this error. Run
  3. Hey Chris, You could disable DDC feature by opt out that option when you customize the IP. Run
  4. Hey Marshall, Glad that you help us out, it works very well! Really appreciate! I kept changing the clock constraint on the xdc file but never be brave eoungh to remove that out. Now I am able to catch up on my project. Run
  5. Hey Guys, Great news and thank you so so much Marshall and Chris! I am going to try it out right now! Once again thank Marshall and Sam for all the works! Run
  6. Oh by the way Chris, is that possible to get more feedback from Sam? Seems like he is one of the best candidates who could help us through.
  7. Hey Chris, I believe you'd better name your port the way dvi2rgb uses which like you mentioned, TMDS_Data_n[2:0], TMDS_Data_p[2:0], TMDS_Clk_p, and TMDS_Clk_n. Otherwise you have to match those names to what you use on the block diagram and of course the names on zybo's port xdc file. So I did the same way you did, name all TMDS ports on block diagram TMDS_Data_n[2:0], TMDS_Data_p[2:0], TMDS_Clk_p, and TMDS_Clk_n. That warning comes out because you manually map the TMDS connections to Zybo's ports while the core set them up as an interface connection but that should be OK (not 100% sure). I d
  8. Hi Marshall, Thank you for your response. I finally figured out that I only need one XDC file for mapping ports instead of including all of those XDC files at the same time, since dvi2rgb core's XDC files will be applied during synthesis. The reason why I need to change dvi2rgb.xdc and dvi2rgb_occ.xdc is because Zybo has a maximum buffer bit clock of 600MHz but those xdc files constrain TMDS_Clk at 165MHz which requires 825MHz buffer bit clock. On the user guide it recommands to constrain TMDS_Clk at 1/5 of the maximum bit clock, which results in 600MHz / 5 = 120MHz pixel clock constraint. Als
  9. Sure Chris, best luck of you too. Hope Jieming would come back soon and give us some tips.
  10. Hey guys, I am working on a same kind of project, trying to use the dvi2rgb ip mentioned. I am trying to get input from the HDMI port and display that through the VGA. I am pretty new to Zybo/Vivado 2014.4 and HDMI stuff so I come up with the following questions: 1. I am trying to set the output to be 720p which means I need a ~75MHz pixel clock from the dvi2rgb ip and the Refclk is set to 200MHz. Does it mean that I need to constrain the TMDS clock to 75MHz on the dvi2rgb.xdc & dvi2rgb_ooc.xdc files? I did the calculation and comes up with a change on the xdc file: "create_clock -period 1