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lijieming last won the day on May 30 2015

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  1. hi hiketen, you may try to reformat your sd card follow this link I met this problem before and finally solved it by change a new sd card.
  2. This problem may occur after failed to program the FPGA in the SDK environment. a simple restart of your computer will solve it. if it still happen, backup your src, delete <your_prj_name.sdk> folder and export hardware again will complately solve it
  3. Hi Chris, Since you are currently developing a Linux embedded system. A Linux host system running on your PC is necessary. dts can not compile into dtb under windows environment. Suggest OS is Ubuntu 14.04 LTS or Cent OS 7 Under Linux environment, the easiest way to handle everything related with zynq and embedded OS is Petalinux solution provided by Xilinx. this tool contains everything you need to make the embedded os to work. Jieming
  4. Dear Chris, 1. Like Run suggested, the error "IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 2 sites." such kind of problem is caused by one or more unconnected external ports on your block diagram. Please check your diagram first to make sure all unused external ports are deleted. (this problem will occur on both 2014.4 and 2015.1) 2. For the DDC part, the HDMI protocol described it clearly that this is a mechanism to let video transmitter and receiver to communicate which each other. By exchanging information, the transmitter could know the detail configuration(ability) of the receiver part (what resolution, frame rate, format of signal the receiver can process). This is a necessary part in HDMI transmission and can not be ignored or deleted. 3. Currently the problem you encountered is how to synthesis the Bi-Directional inner control ports into a signal Bi-Di external port. To solve this problem, first you should understand what is a bi-di port and its mechanism(I am sure you know it). Secondly, in Xilinx ISE, three bi-di control ports can be easily synthesized together by adding a constrain command in the .ucf file. In vivado the goal can't be achieved by only modify the .xdc. In my way, i directly modified the DVI2RGB ip core, the top_module i mentioned is the top module of the ip core (the dvi2rgb.vhd file). The core is written by VHDL, modify the following: a. In the port description change DDC ports to below -- Optional DDC port DDC_SDA : inout std_logic; DDC_SCL : in std_logic; b. add HPD and CEC port in the end of port def HDMI_HPD : out std_logic; HDMI_OUT_EN : out std_logic c. in the behavioral part add signal def and logic architecture Behavioral of dvi2rgb is ....... signal hpd : std_logic; ....... begin DDC_SCL_I <= DDC_SCL; DDC_SDA <= DDC_SDA_O when DDC_SDA_T = '0' else 'Z'; DDC_SDA_I <= DDC_SDA; HDMI_OUT_EN <= '0'; HDMI_HPD <= hpd; ....... d. in the TMDS_ClockingX call add port "hpd" TMDS_ClockingX: entity work.TMDS_Clocking generic map ( kClkRange => kClkRange) port map ( ......... hpd => hpd ); f. in the TMDS_ClockingX module(vhd file) add "hpd" def. this will active the HDMI transmittion only after the sink core has been locked entity TMDS_Clocking is Generic ( kClkRange : natural := 1); -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5 Port ( ......... hpd : out std_logic); end TMDS_Clocking; architecture Behavioral of TMDS_Clocking is .......... begin hpd <= aDlyLckd; ......... the above is all you need to make this core compatible with HDMI. after modification -> save -> repackage ip core 4. All you need in your project xdc file is really sample if modification has been done inside ip core. below is my xdc set_property PACKAGE_PIN H16 [get_ports HDMI_CLK_P] set_property PACKAGE_PIN H17 [get_ports HDMI_CLK_N] set_property PACKAGE_PIN D19 [get_ports {HDMI_D_P[0]}] set_property PACKAGE_PIN C20 [get_ports {HDMI_D_P[1]}] set_property PACKAGE_PIN B19 [get_ports {HDMI_D_P[2]}] set_property PACKAGE_PIN D20 [get_ports {HDMI_D_N[0]}] set_property PACKAGE_PIN B20 [get_ports {HDMI_D_N[1]}] set_property PACKAGE_PIN A20 [get_ports {HDMI_D_N[2]}] set_property IOSTANDARD TMDS_33 [get_ports HDMI_CLK_*] set_property IOSTANDARD TMDS_33 [get_ports HDMI_D*] set_property PACKAGE_PIN G17 [get_ports HDMI_SCL] set_property PACKAGE_PIN G18 [get_ports HDMI_SDA] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SCL] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_SDA] set_property PACKAGE_PIN E18 [get_ports HDMI_HPD] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_HPD] set_property PACKAGE_PIN F17 [get_ports HDMI_OUT_EN] set_property IOSTANDARD LVCMOS33 [get_ports HDMI_OUT_EN] create_clock -name sysclk -period 25 -waveform {0 12.5} [get_ports HDMI_CLK_P] this is all you need for your project. Jieming
  5. Hey Guys, Glad to see your progress of the video project. Sorry for coming back late (have been on vacation aboard last week). Still willing to help with anything Jieming
  6. Hi Chris, It's so happy to see your post since I am just finished a prototype project that very similar to yours except the video will not transmit by eth but being processed on board. based on my experience I give the following answers to your ques: 1.You thought is absolutely right (my project worked well now just based on this architecture) 2.No VTC is needed at the final stage. But it's strongly recommend you add a VTC during debugging. During my experiment I find out even all of the video source I used marked as "1080p 60p", the video timing is still varies very much due to different recording product and brand. 3.Both the DVI2RGB core and the hdmi_rx core you mentioned before in the "instructables" project works. In fact if you go through the code of the two core you may find out they are almost the same. However (PAY ATTENTION HERE), in vivado, inout port no longer automatically being synthesised to a single port. you have to make a little change at the top level module of the core like HDMI_SDA <= HDMI_SDA_O when HDMI_SDA_T = '0' else 'Z'; HDMI_SDA_I <= HDMI_SDA; of course for the DVI2RGB core you also need to add hdmi support pin (HPD, OUT_EN) but if you go through the hdmi_rx core you'll find the logic of them is really simple There is still something need to care, In the DVI2RGB core's documentation, it says clearly that the input clock should be constraint based on the specific chip. the hdmi_rx core only support 720p video source and DVI2RGB core support up to 1080p video source but the ZYBO is using XC7Z010 -1 chip the MAXBUIO is 600MHZ. 1080p 60p needs 148.5MHZ pixel clock that is around 750 MHZ bit clock. That means if you want to implement the 1080p decoder, the timing requirement will sure fail. But in my experiment. even thought the design fail to meet timing constrains. The 1080p video from my Macbookpro's video card can still be recognised correctly (However the 1080p video from GoPro's hdmi can't be decoded correctly). 4.In my project, the VDMA driver is used, you can take the Zynq Base TRD 2014.4 as a really good reference. All the driver configuration and usage examples has been included in it. OK, In the final, speaking frankly, It's not an easy road (for developing such a project). you'll meet tons of issues and need to read tons of docs(datasheets userguides refApps) later. Feel free to post any further questions here so as to see if I could give you any help. Jieming
  7. hi Hiketen, The hands on tut has already a kind of "expired". after you make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi- xilinx_zynq_defconfig you can compile the kernel straightforward make ARCH=arm CROSS_COMPILE=arm-xilinx-linux-gnueabi-