xilinx.fpga.user

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  1. Hi Zygot: Thank you so much for your feedback. As you had suggested I have tried to focus on debugging at packet level and observe the interfaces. Below are the things I have tried and my observations. 1) MDC/MDIO Interface: I probed MDC/MDIO interface of the PHY using an oscilloscope. As the PHY is different (Realtek on Genesys-2 board instead of Marvell on Xilinx board) I wanted to make sure that the change I had made in device tree to show the new device (PHY) address is working correctly. Observing the scope traces I was able to confirm the PHY is being addressed cor
  2. Hello Jpeyron, Cprian & Zygot: Thank you so much for your feedback. Following your suggestions I have completed the steps below. 1) Verified that XDC file and port mapping is correct. 2) Looked at the reference design from Digilent which uses an ethernet port. In this design I looked for timing constraints on RGMII pins. I did not see any specific timing constraints. Other sections of design like the memory interface are working. The only missing piece is the ethernet interface. 3) The Software I am running on our board is provided by Analog Devices. Please refer
  3. Hello: I am unable to get Ethernet interface to work on Genesys-2 in my design which is migrated from a Xilinx board. I have a Microblaze based design that I am trying to port to Genesys-2 Board. This design is working on Xilinx KC705 evaluation board which uses the same Kintex-7 FPGA as Genesys-2. On this design I have Ethernet interface, DDR3 Interface and some other peripherals. We are using Linux for this design. This design was originally developed by another company and was used for evaluating their chip. It was developed on Xilinx evaluation board KC705. This company does no