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Everything posted by vicentiu

  1. vicentiu

    How to boot linux via sd card in zedboard

    Hello, Please reference the following documentation:
  2. vicentiu

    sdsoc_opencv error

    Have you read the following SDSoC documentation from Xilinx?
  3. vicentiu

    sdsoc_opencv error

    SDx contains SDSoC as described here.
  4. vicentiu

    sdsoc_opencv error

    In this post, there are 18 steps. In which step number are you getting errors?
  5. vicentiu

    sdsoc_opencv error

    The computer where you have SDSoC installed.
  6. vicentiu

    sdsoc_opencv error

    Which step are you referring to when you say "create the opencv project"?
  7. vicentiu

    sdsoc_opencv error

    What kind of interface does your camera have? USB, HDMI or MIPI? Please attach an archive of the sdx project also. Have you tried compiling your project for your host machine?
  8. vicentiu

    sdsoc_opencv error

    You don't need to re-include the opencv library if you follow the steps above. What is this "same error" you are referring to?
  9. vicentiu

    sdsoc_opencv error

    How is the webcam connected to the board? USB, HDMI or MIPI port? What errors are the opencv headers showing? Please attach full log.
  10. Hello, The Xilinx guide you mentioned is relevant for versions starting with 2018.1. Since our Petalinux project on github is using 2017.4, the procedure is a single command. $ cat bitstream.bit > /dev/xdevcfg Here is the reference for versions 2017.4 and earlier:
  11. vicentiu

    sdsoc_opencv error

    Are you referring to step 4? Are you getting an error at that step? We don't know what you are referring to here. There are two reasons why you might not see filter2d Live I/O: You didn't download the right revision platform. Make sure you download this platform. If you have some other platform already downloaded for Zybo-Z7 you need to first remove it from the IDE. There is a small chance there is some IDE error. In this case, you need to contact Xilinx for support.
  12. vicentiu

    sdsoc_opencv error

    For the "sample application" mentioned in step 12, make sure it is an application that depends on xfopencv, such as the Simple Filter2d Live I/O. Let us know if you get stuck in any of the steps.
  13. vicentiu

    sdsoc_opencv error

    I am confused. In this post you mentioned you were able to successfully build the default SDx example vector add project. Can you provide the link to the github project you are referring to?
  14. We haven't been able to reproduce your issue. We added a Quad SPI in Vivado block design 2017.4 and 2018.2 and the default is standard.
  15. vicentiu

    Petalinux on Cora

    We're glad you got it to work. You're right that upgrading all the projects takes a significant amount of work, and we do have plans to upgrade but can't make any promises about the timeframe. thanks
  16. vicentiu

    Zybo-Z7 Serial Port not working

    Hi @rmd91, Just wanted to confirm that you followed these instructions and were not able to build a petalinux image? It mentions doing a git clone with --recursive, in which case you should have all the external git repos to build.
  17. vicentiu

    how to link device tree bin to u-boot binary?

    Please follow these instructions to build a petalinux image for Zybo. To build just u-boot, run petalinux-build -c u-boot The command in the document that packs BOOT.BIN is petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot
  18. Can you give more detail on what you have tried to connect to Pynq? You did a direct connection between your computer and Pynq? What does 'ifconfig' on Pynq look like? What does network interface setup look like on your computer? Can you ping in either direction?
  19. We just tried with the image from our PYNQ reference page and it worked fine. Did you try pressing the ENTER key once you opened the terminal to see if you get a prompt? You don't need to wait until the system boots to open the terminal connection. How do you know the system booted?
  20. vicentiu

    Date/Time Clock?

    You can use our Pmod RTCC and follow the guidance in this comment. Alternately, if you have a network connection, add NTP to the rootfs and the clock will update automatically.
  21. vicentiu

    [ORIGINAL ZYBO] Using the board in modern workflows

    Hello, We don't have any plans to make upgrades for the Zybo board, but we will accept pull requests if others decide to do so. thanks
  22. vicentiu

    PCAM elf on PetaLinux from SD card

    I ran most of the commands you ran and booted successfully. I'm connecting with TeraTerm from Windows. I didn't run the following: It looks like you want a rootfs. I booted with initramfs. if you want rootfs, you'll need to run petalinux-config to change root filesystem type and also change the bootargs. The details are in the "Configure SD rootfs" section of the project. Make sure you clean the project after switching from initramfs to rootfs (or vice versa). We noticed that if you make the switch and rebuild without cleaning, it will stay stuck in that same place: Starting kernel....
  23. vicentiu

    PCAM elf on PetaLinux from SD card

    Are you using minicom to connect to the serial console? If yes, try connecting with Putty. We've noticed the same issue with minicom, and terminal output worked fine once we switched to Putty.
  24. vicentiu

    device-tree (spartan 6)

    We haven't come across this error before. You can look at the context around the panic in memblock.c. It could be some incompatibility, a misconfiguration of the kernel, device tree or memory ip(s) in EDK design.
  25. vicentiu

    PCAM elf on PetaLinux from SD card

    We have a PCAM demo in the Petalinux-Zybo-Z7-20 project. The PCAM support is not included in the Petalinux-Zybo-Z7-10 project because they were intended for SDSoC and the FPGA in the Z7-10 is too small for SDSoC usage. We modified the Z7-20 Vivado project to work on the Z7-10 (system.hdf file attached.) Follow these steps to have PCAM support on the Z7-10. Git clone Petalinux-Zybo-Z7-20 Unzip the attached system.hdf file in a folder and include the system.hdf in the unzipped folder itself. Copy & replace the folder contents into project-spec/hw-description of the petalinux project. Build the image with the petalinux-build command Follow the PCAM instructions at the bottom of the readme for Petalinux-Zybo-Z7-20 FYI, here are the steps to modifying the Z7-20 Vivado project to work on the Z7-10. A SDSoC license is needed for generating the bitstream. Download the Zybq-Z7-20-base-linux project from and unzip. Download the Vivado library from and unzip it in the Zybq-Z7-20-base-linux project, in the \repo\vivado-library folder. Make sure you have the Zybo Z7 board support files in your Vivado installation. If you don’t have them, download them from, unzip the downloaded file, and copy the contents from the \vivado-boards-master\new\board_files folder to your Vivado 2017.4 installation folder (e.g. C:\Xilinx\Vivado\2017.4\data\boards\board_files). Open Vivado 2017.4, select Tools -> Run Script and run the create_project.tcl script from the \proj folder inside the Zybq-Z7-20-base-linux folder. Change the target board in Viado, by selecting Settings -> Project Device -> Zybo Z7-10 -> OK. Save the project. You will need to regenerate the IPs used in this project, due to the board change. Tools -> Report IP Status -> Upgrade Selected. The Zybo Z7-10 board has one less RGB LED than Zybo Z7-20 boards. Therefore, you will need to do several change to the project: In the Zybo-Z7-Master.xdc file, comment out the lines referring to RGB LED 5: #set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { pwm_rgb[2] }]; #IO_L18N_T2_13 Sch=led5_r #set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { pwm_rgb[1] }]; #IO_L19P_T3_13 Sch=led5_g #set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { pwm_rgb[0] }]; #IO_L20P_T3_13 Sch=led5_b In the same XDC file, change the indexes of the lines referring to RGB LED 6, so they look like this: set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { pwm_rgb[2] }]; #IO_L18P_T2_34 Sch=led6_r set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { pwm_rgb[1] }]; #IO_L6N_T0_VREF_35 Sch=led6_g set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { pwm_rgb[0] }]; #IO_L8P_T1_AD10P_35 Sch=led6_b In the project block diagram, double-click on pwm_rgb IP and change the Number of PWMs from 6 to 3. Select OK and save the project. Also in the project block diagram, double click on the output from the pwm_rgb IP (pwm_rgb signal), select Properties and then change the LEFT parameter from 5 to 2. Save the project. It may have happened that no top-level wrapper was generated for your project. If so, right-click on the system_i block diagram and select Create HDL Wrapper… Then right-click on the newly-created wrapper and select Set As Top. Save the project. You can now generate the bitstream and you should not see any issues while doing that.