Venkat

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About Venkat

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  1. Hi @JColvin, I am using Vivado Design Edition. I agree with @zygot, that the demo design need to be free from tool version. If this is tool specific, then why not Digilent provides the Source Code for the Demo board itself.? Is there a way for you or someone @ Digilent to run the Demo with Vivado 2015.4 and provide the Source Code as attachment here. I believe I have seen a thread mentioning about the Source Code Zip file attachment, somehow I couldn't see it. Regards, Venkat
  2. Hello @BogdanVanca, I am using Vivado 2018.2 version. Regards, Venkat
  3. Hi , I have purchased recently Genesys2 FPGA Board and trying to re generate the bit file OOB project. I have followed the below steps mentioned in the Genesys 2 Out of Box Demo Tutorial: 1. Downloaded the project. 2. Installed the Vivado board file for Genesys2 3. Generated OOB project by sourcing the tcl script in Vivado. When tried to to Genearate bitstream I get the following error: Also when tried to synthesize I am getting the following error: Looks like there are no source files present in the project repository. Where to get the Genesys2 OOB Project source files ? Appreciate for your time and help. Regards, Venkat
  4. Hi @attila, With your suggestions, now able to run at different frequencies ( > 1KHz). Thanks a lot. Regards, Venkat
  5. Hi @attila, I see the output of LA is matching only when set to certain frequencies. 1. (in my example above, the freq is 1e8 = 100MHz) and output is matching: Frequencey: 100000000.0 PG Channel-0 data: 10101110 11010011 10010010 11111111 LA Channel-0 data: 10101110 11010011 10010010 11111111 00000000 2. When the frequency is changed to 1MHz i.e. 1e6, output is not maching (looks like 1st sample is missing) Frequencey: 1000000.0 PG Channel-0 data: 10101110 11010011 10010010 11111111 LA Channel-0 data: 01011101 10100111 00100101 11111110 00000000 3. When the frequency is changed to 1KHz i.e 1e3, output is not matching(again looks 1st sample is missng) Frequencey: 1000.0 PG Channel-0 data: 10101110 11010011 10010010 11111111 LA Channel-0 data: 01011101 10100111 00100101 11111110 00000000 I have used the above modified script with different frequencies. Could you please check at your end if possible by running the same script with 1MHz or 1KHz. Thanks a lot. Regards, Venkat
  6. Hi @attila, It worked for me with the modified script provided by you. I see the major change is : 1. LA samples are increased by 8 ( this should be go as i can ignore the last 8 samples when compare to the PG) 2. DigitalInSampleFormatSet to be c_int(8) 3. DigitalInStatusData data_array type I have tried few times and all the time it worked. Next thing I need to increase the number of channels and repeat cnt etc. Once again thanks a lot. Regards, Venkat
  7. Hi Attilia, Thanks your suggestion for using the dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDigitalOut). Looks like this change solves the +/-1 trigger position. Now the LA capture data is matching with PG data at the trigger position. Some how it still doesn't match last few bits (mismatch varies from run to run). Please see below different run results. Run_1: (3 bit mismatch) PG Channel-0 data: 01110101 11001011 01001001 11111111 LA Status Check STS VAL: 2 Acquisition finished LA Channel-0 data: 10101110 11010011 10010010 11111000 Run_2: (2 bit mismatch) PG Channel-0 data: 01110101 11001011 01001001 11111111 LA Status Check STS VAL: 2 Acquisition finished LA Channel-0 data: 10101110 11010011 10010010 11111100 Run_3: (5 bit mismatch) PG Channel-0 data: 01110101 11001011 01001001 11111111 LA Status Check STS VAL: 2 Acquisition finished LA Channel-0 data: 10101110 11010011 10010010 11100000 Attached is the copy of the script I am using at my end. If you could look into this (also you should be able to use as is), and let me know if there is any issue with my script, that would be great. Regards, Venkat digilent_pg_to_la.py
  8. Hi Attila, Just wanted to update on the LA behavior: Problem was not last 4 bits. It can be 3 bits or 5 bits.. as shown below PG Channel- 1 data: 01110011 11000111 11101110 00011110 LA Status Check Acquisition finished LA Channel-1 data: 11001110 11100011 01110111 01100000 Regards, Venkat
  9. Hi Aiila, First of all very big thank you for responding so quickly and promptly. As you mentioned I have modified/used: dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn) dwf.FDwfDigitalInSampleFormatSet(hdwf, (2)) dwf.FDwfDigitalInTriggerPositionSet (handle, c_int(4*8-1)) #4 bytes are sent on PG and need to be captured on LA And increased data to be sent to 4Bytes cSamples = 32 When DigitalInTriggerPositionSet to 32, LA read buffer doesn't have the 1st bit sent on PG. Hence I have set the value to 31, LA read buffer contains the 1st bit sent on PG. With the above settings and all other settings mentioned in the origital thread, I see last 4 bits either not captured on LA or not stored in to DigitalInBuffer as in below: PG Channel- 1 data: 01110100 11001011 01001001 11100011 LA Status Check Acquisition finished LA Channel-1 data: 00101110 11010011 10010010 11000000 Could you please clarify 1) why 1st bit is missing in the capture when FDwfDigitalInTriggerPositionSet to 32 (exact cnt) 2). why the last 4 bits are missing in the capture. Regards, Venkt
  10. Hi, I am new user of DD. I am developing python script to send custom data on pattern generator and receive it on logic analyzer and then do data integrity check (as of now dumping the data to csv file and later need to modify to compare the data). when run the Python script (see below) , I see all '0' in csv file. Appreciate if anybody provide me insight on how to achieve this task. Below is pattern generator related code: channel = 0 dwf.FDwfDigitalOutEnableSet(hdwf, channel, c_int(1)) dwf.FDwfDigitalOutTypeSet(hdwf, channel, DwfDigitalOutTypeCustom) cBits = 16 rgdData = (2*c_byte)(*[0x12,0x34]) dwf.FDwfDigitalOutDataSet(hdwf, channel, byref(rgdData), c_int(cBits)) dwf.FDwfDigitalOutRunSet(hdwf, c_double(2*8/1e8)) # 160ns = 2*8 bits /100MHz = 16 bits * 10ns dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(1)) # once print('PG Setup Done: Channel ',channel) And below is Logic Analyzer related code: dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDigitalIn) dwf.FDwfDigitalInTriggerSet(hdwf, 0,0,0xFFFF,0xFFFF); dwf.FDwfDigitalInTriggerAutoTimeoutSet(hdwf, c_double(10.0)); #sample rate = system frequency / divider, 800MHz/8 = 100MHz sample rate dwf.FDwfDigitalInDividerSet(hdwf, c_int(8)) # 16bit per sample format dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(16)) # set number of sample to acquire cSamples = 16 #rgwSamples = (c_uint16*cSamples)() rgwSamples = (c_uint8*cSamples)() dwf.FDwfDigitalInBufferSizeSet(hdwf, c_int(cSamples)) Both LA and PG are configured: # begin acquisition # Enable LA dwf.FDwfDigitalInConfigure(hdwf, c_bool(0), c_bool(1)) # Enable PG dwf.FDwfDigitalOutConfigure(hdwf, c_int(1)) Below is Acquisition code: while True: dwf.FDwfDigitalInStatus(hdwf, c_int(1), byref(sts)) print ('STS VAL: ', str(sts.value)) if sts.value == stsDone.value : break time.sleep(1) print ('Acquisition finished') And below is read data code: # get samples, byte size #dwf.FDwfDigitalInStatusData(hdwf, rgwSamples, 2*cSamples) dwf.FDwfDigitalInStatusData(hdwf, rgwSamples, 1*cSamples) dwf.FDwfDeviceCloseAll() For the time being writing to csv file: f = open("record.csv", "w") for v in rgwSamples: f.write("%s\n" % v) f.close() Regards, Venkat digilent_examp.py