mwingerson

Digilent Staff
  • Content count

    190
  • Joined

  • Last visited

  • Days Won

    9

mwingerson last won the day on November 10 2015

mwingerson had the most liked content!

5 Followers

About mwingerson

  • Rank
    Mr. 11-bit.

Profile Information

  • Gender
    Male
  • Location
    Pullman, WA

Recent Profile Visitors

2326 profile views
  1. mwingerson

    AnalogShield with Due

    Hello Luc, Unfortunately, the Arduino Due is not a supported board for the library. There was some community support and I wrote the framework for the Adruino Due but never got my hands on one to confirm it working or not. As it sounds, it is currently not working. I will update the to do list to reflect that the library is currently not working with the Arduino Due. Best of luck, Marshall
  2. mwingerson

    How to install Yocto Project 2.1 on ZYBO

    Hello Haruto, We do not have a Yocto build for the ZYBO yet. It is in the works but the release date is unknown. Marshall
  3. mwingerson

    ZYBO device locked license - worthless?

    hey ks0ze, I talked to my supervisor and he said that he is escalating the issue. To the best of his knowledge the license that you paid for is exactly the same as the webpack license but locked to the ZYBO. I guess we pulled the license from the store some time ago but apparently after you bought your license. From James it sounds like we are offering RMAs for unused licenses now so if you haven't redeemed it then please contact our support email. Otherwise the issue is being brought up to the right people. Best, Marshall
  4. mwingerson

    Cmod C2 dev kit

    Hey James, This can be a long and painful road but here are the requested resources. programmers: http://store.digilentinc.com/jtag-hs2-programming-cable/ http://store.digilentinc.com/jtag-hs3-programming-cable/ The IDE will be Xilinx ISE 14.7: http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html VHDL resources http://store.digilentinc.com/digital-design-using-digilent-fpga-boards/ http://www.asic-world.com/
  5. mwingerson

    ZYBO device locked license - worthless?

    Hello ks0ze, Sorry for the delay. Originally this license was supposed to grant you access to a lot of of IP cores and a couple features that weren't included in the standard Webpack license. Since then a lot of features and IP cores were added to the Webpack license diminishing its value. Last time I looked at the usefulness of this license the big value that you were getting was Chipscope. Since I have not kept up with what Xilinx has released under the Webpack license, I will contact Xilinx to confirm what features are included with that license and I will talk with our marketing department to clarify this point on the product description. More than anything, we don't want you to feel 'scammed' and if there is no value associated with this license then we need to pull that product and try to make amends with our customers who bought it. Specifically, what license did you buy? The one in the Zybo Accessory Kit, Xilinx Vivado Design Suite Voucher for Zybo or the Zynq SDSoC Development Voucher? Marshall
  6. mwingerson

    ADC SPI Interface

    Hello Garrett, I am sorry but we cannot write code for every request that we get. I do know some excellent resources that I used when learning VHDL and Verilog. Here is a Digilent associated class that teaches basic digital logic and provides some Verilog examples: http://www.eecs.wsu.edu/~ee214/announcement.php Here is a great general site for learning VHDL or Verilog (I used it a ton): http://www.asic-world.com/index.html If you prefer a book, here is one written by Digilent (I found it good and worth the money): http://store.digilentinc.com/digital-design-using-digilent-fpga-boards/ Good luck! Marshall
  7. mwingerson

    UDB IC4 Pin 18-26 Short

    Hi Frank, Unfortunately, we designed and produced the UDB board for Microchip and are not allowed to distribute the schematic. I am unaware of the reason why the schematic is closed source. You could try to contact Microchip to see if they will distribute the schematic but we cannot. I did dig through the schematic and found that the IO pins are all wired directly from the IC4 socket to the J6 header. The only reason why you should be seeing ground on those pins are because the PIC is pulling the pins to ground. To confirm this for yourself, you can measure the resistance between the IC4 socket and the corresponding pins on J6. With the board unpowered and the PIC MCU removed. The resistance should be very low between corresponding pins and open between non-corresponding pins. Hope this help and good luck! Marshall
  8. mwingerson

    Use Microblaze performance monitoring engine from AXI4Lite

    Unfortunately, this is a topic that is outside of our capabilities. Please try to contact Xilinx over at their forum. Best of luck! Marshall
  9. Here is a project that Sam uploaded. The project that you are looking for is Mem_Loader. https://reference.digilentinc.com/_media/genesys/genesys_bist_clean.zip Best of Luck! Marshall
  10. mwingerson

    Anvyl demo documentation

    The keypad-seven segment demo is strangely complex but the source code for it is fairly straightforward. I drew a quick block diagram to figure out what is happening. A simple explanation: 1. col_cnt is counting from 0b00 to 0b11 2. the decoder changes the number to an inverted bit location IE: 0b01 -> 1101 3. The decoded signal from 2 is passed to the keypad_decoder and out of the chip to the keypad itself. 4. The keypad_decode module analyzes the two incoming signals and produces the resulting value for the location of the button that was pressed. The value is passed to the BRAM 5. The key_detect module just finds when a key is pressed and enables the write enable on the BRAM 6. The seven segment decoder is enabled by an external switch 7. The seven segment decoder requests data from the BRAM at an address and the BRAM returns the value stored at the requested location. 8. Finally the seven segment decoder displays the values on the seven segment display. Hope the helps! Marshall
  11. mwingerson

    Vivado Launching SDK "Importing Hardware Specification" error

    that is a frustrating error for a simple solution. Glad you figured it out and thanks for posting back! Marshall
  12. mwingerson

    Genesys 2 current measurement problem

    I try to troubleshoot as much as I can in simulation since troubleshooting in hardware is slow and painful. It is a lot better using Chipscope, if you have a license. Here is a demo for simulating a custom IP core in Microblaze. https://reference.digilentinc.com/zybo/custom_ip_simulation It isn't exactly what you are trying to do but the steps on simulating a Microblaze project are there. In simulation you should be able to confirm the design and program. Most importantly, you want to see that the IIC lines are changing as expected with your design and program. Then move to troubleshooting incoming data. I would route incoming IIC data to the uart either in software or hardware. Dealer's choice. Best of luck! Marshall
  13. mwingerson

    basic Linux component to boot up

    Hello Phong, I was writing the prebuilt Linux demo and got pulled onto other projects. I'll get back to it but it may take a little time. One of the best starting points would be here: https://reference.digilentinc.com/zybo:zybo:zybotguide This guide will get you a GUI based Linux setup on the ZYBO. Best of Luck, Marshall
  14. mwingerson

    ZedBoard VCCAUX vs. VCBATT_0

    Hello Jude, You have some challenging questions. J16 is a header so a secondary battery can keep the security section of the RAM active without the primary 12V source. To do this, R187 need to be removed otherwise the secondary battery will be powering a good chunk of the board and has a high chance of damaging some components. In this case the amount of power that will be used through VCCBATT_0 pin should be very small. I looked through the documentation but I could not find how much current will be pulled through VCCBATT_0 with or without a 12V source. I would suggest contacting Xilinx support or forums to find a more solid answer. Best of luck, Marshall
  15. mwingerson

    Appeal for a Nexys4DDR project example using MIG in ISE

    You bring up some valid points. I guess I just have gotten use to not having the instantiate templates and I primarily use Verilog so I didn't notice the VHDL issue. I didn't know that ISE was working in W10. is it the same fix a that allowed ISE to work in W8? I agree with Andrew. Use the SRAM to DDR component. It will save a lot of time. Best of Luck, Marshall