kwilber

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Everything posted by kwilber

  1. You need to install the digilent board files. The procedure is detailed in section three of this wiki page.
  2. The error message is not very obvious. In the guide it says "If it doesn’t say Bus Width: 4-bit, then your SD-Card failed to be detected or was stuck in an incorrect mode. You should hit the CPU_RESET and/or power off to retry"
  3. The bit file in QSPI only implements the system hardware and a simple first stage bootloader. Very similar to how pc's have a bootloader in rom but load the actual operating system from disk. The SD card will hold the actual linux file system and is just like a disk drive in your pc. There are 4 partitions on the card. First, there is a FAT32 partition that has boot.bin. This is a more capable loader that knows about the structure of the sd card and can locate and read the linux kernel. A second ext4 formatted partition holds the kernel. A third partition is for swap space. A fourth ext4 partition is used for the rest of your file system. The startup guide explains how to create the sd card. It begins at the section "READ THIS WARNING (!)" and ends at "Remote console installation".
  4. Hello @aeon20 I replied to your PM but will also reply here so others can benefit. I followed the getting started guide and used the "standalone installation" option. On my Nexys A7 100T, I made sure sw1 was on and the others were off. JP1 was set to QSPI and JP2 was set to USB. I attached a usb keyboard and vga monitor. I initially left the sd card out so I could observe the behavior. The read from the sd failed as expected. The quickstart mentions that a reported bus width other than 4 bytes is an error. 0: 0 1: 1 2: 1 3: 1 800: 1e 801: 0 802: 0 803: 0 Selftest iteration 1, next buffer = 0, rx_start = 4000 Selftest matches=2/2, delay = 9 Selftest iteration 2, next buffer = 1, rx_start = 4800 Selftest matches=4/4, delay = 9 Selftest iteration 3, next buffer = 2, rx_start = 5000 Selftest matches=8/8, delay = 9 Selftest iteration 4, next buffer = 3, rx_start = 5800 Selftest matches=16/16, delay = 16 Selftest iteration 5, next buffer = 4, rx_start = 6000 Selftest matches=32/32, delay = 31 Selftest iteration 6, next buffer = 5, rx_start = 6800 Selftest matches=64/64, delay = 60 Selftest iteration 7, next buffer = 6, rx_start = 7000 Selftest matches=128/128, delay = 119 Selftest iteration 8, next buffer = 7, rx_start = 7800 Selftest matches=187/187, delay = 173 lowRISC boot program ===================================== Hello LowRISC! Tue Aug 14 10:40:47 2018: Booting from FLASH because SW1 is high .. u-boot based first stage boot loader MMC: mmc created at 86800248, host = 86800200 lowrisc_sd: 0 Device: lowrisc_sd Manufacturer ID: 0 OEM: 0 Name: Bus Speed: 5000000 High Capacity: No Capacity: llu BytesBus Width: 1-bit Next I inserted the sd and reset the board. The boot process went pretty much as described in the guide. It eventually left me at a login. I logged in as root and followed the firstboot procedure. Debian GNU/Linux buster/sid lowrisc tty1 lowrisc login: root Linux lowrisc 4.18.0-gc81ff0d #48 Thu Oct 18 16:00:24 BST 2018 riscv64 The programs included with the Debian GNU/Linux system are free software; the exact distribution terms for each program are described in the individual files in /usr/share/doc/*/copyright. Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent permitted by applicable law. [ 258.760000] systemd-logind[1160]: New seat seat0. This is the firstboot script. It will display only once Set the superuser (root) password below Enter new UNIX password: Retype new UNIX password: passwd: password updated successfully Creating normal user lowrisc ... Adding user `lowrisc' ... Adding new group `lowrisc' (1000) ... Adding new user `lowrisc' (1000) with group `lowrisc' ... Creating home directory `/home/lowrisc' ... Copying files from `/etc/skel' ... Enter new UNIX password: Retype new UNIX password: passwd: password updated successfully Changing the user information for lowrisc Enter the new value, or press ENTER for the default Full Name []: Room Number []: Work Phone []: Home Phone []: Other []: If no switches are set you would see lowRISC boot program ===================================== Hello LowRISC! Tue Aug 14 10:40:47 2018: Turn on SW0 for gdb loading, SW1 for SD-card loading, or SW2 for Ethernet loading if sw0 is set, the display clears and no other activity occurs, presumably it is waiting for debugging commands to come in via the uart. If sw2 is set you would see (i do not have the ethernet port connected) lowRISC boot program ===================================== Hello LowRISC! Tue Aug 14 10:40:47 2018: Booting from Ethernet because SW2 is high .. Max file size is 17146368 bytes MAC = eee1:e2e3e4e0 MAC address = ee:e1:e2:e3:e4:e0. eth0 MAC : EE:E1:E2:E3:E4:E0 Sending DHCP_DISCOVERY Waiting for DHCP_OFFER
  5. This link explains why the xadc is being included when you use the mig. https://www.xilinx.com/support/answers/51687.html
  6. Xilinx had a thread a few years ago that discussed this. They describe how you can get by without a level shifter. There is also an old Digilent forum thread that discusses a similar project using a Basys3.
  7. According to the HCSR04 datasheet, it requires 5v for Vcc. The zybo reference manual shows, in section 16, pmods only have 3.3 v on pins 6 and 12. You would need a level shifter and a 5v supply powering the HCSR04.
  8. This core and this core are pretty easy to use and do not require a microblaze or zynq. Zynq based boards typically have the PHY connected to the PS. This makes it a bit difficult to use the PHY from the PL. There is a Xilinx wiki that describes accessing the PHY from the PL.
  9. You can find an example of driving the Cora RGB leds here. The demo has the rgb leds as ports on the top level design and uses simple logic to control them. If you want to control them from the PS, you could use an AXI GPIO block or an AXI PWM block.
  10. The example project you referenced is for a different manufacturers board (the Blackboard) and they have an rgb led on the mio bank. The Cora schematic you linked shows the rgb leds are on bank 35 on sheet 8.
  11. You downloaded the zip for the repo. The .xpr file is specific to the version of vivado used to create a project. Since the repo can be used with different versions of Vivado, an.xpr file is not provided. You need to use the Release zip from the Releases page. Note that you must use the version of Vivado that matches the release zip. Complete instructions for running the demo are given in the "Demo Setup" section of the README.md file.
  12. Just curious, does the elf file you are trying to load use interrupts? The second link explains how the large gap between the interrupt vector table and the start of the program results in huge file sizes.
  13. Here are two additional articles I have read on the technique being applied to a zynq. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842065/Zynq-7000+AP+SoC+Low+Power+Techniques+part+5+-+Linux+Application+Control+of+Processing+System+-+Frequency+Scaling+More+Tech+Tip https://github.com/tulipp-eu/tulipp-guidelines/wiki/Dynamic-voltage-and-frequency-scaling-(DVFS)-on-ZC702
  14. Is this a simple a-b vs b-a thing? Addition is commutative sub subtraction is not.
  15. I have previously used this tutorial and did not experience 2 minute boot times. Perhaps you could run through the tutorial and see how it behaves on your board. There was also an old Xilinx answer record about eliminating large gaps in the s-record file. The steps outlined in there might help.
  16. Vivado is complaining that there are active (not commented) pins in the constraint file that do not have matching port names in your design. Open your design_1_wrapper.v file and reconcile the port names specified there with the constraints file. It is not uncommon to have to change the name of a pin in the constraints file to match the port name in the wrapper. This could happen for example if you used "Make external" on an i/o pin from an IP block. One thing that has helped in the past was to delete the top level wrapper and regenerate it. Sometimes when you make pins external after generating the wrapper, there can be inconsistencies between port and pin naming. Xilinx UG903, page 42 and following elaborates on the scoping mechanism Vivado uses.
  17. When you installed Vivado, did you include support for Artix7 devices? You can check using the "Add Design Tools or Devices" command in the help menu. I apologize that I can not paste screen snips, but I have reached the limit the forum allows for my attachments.
  18. Have you set up the Arty and Olimex ARM-USB-TINY-H as detailed in chapter 2 of this document? It looks like the TINY-H connects to the Arty via pmod JD.
  19. One of the things those new to Xilinx struggle with is the terminology. I think this thread is a good example of that. The OP was thinking in terms like schematic and symbol whereas the Xilinx concepts are block design, IP, packaging and rtl module. While @zygot is correct that DocNav is the ultimate reference, I found my DocNav searches became more effective as I became more familiar with Xilinx terminology.
  20. A couple Xilinx quick take videos to give you an overview. https://www.xilinx.com/video/hardware/referencing-rtl-modules-for-vivado-ip-integrator.html https://www.xilinx.com/video/hardware/packaging-custom-ip-integrator.html The IP packager user guide https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1118-vivado-creating-packaging-custom-ip.pdf And chapter 12 in the IPI guide https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug994-vivado-ip-subsystems.pdf
  21. This article series evaluated the lowRisc and SiFive cores. I went through the lowRisc getting started guide on my Nexus A7 and it worked as advertised.
  22. @Ahmed Alfadhel, One other thing to note is your scope was AC coupled in your pictures so you were "seeing" a bipolar waveform of -1.28v to +1.28v. If you had DC coupled, the waveform on the scope would have shifted up and you would have observed the 0v to 2.5v the DA was outputting. To get an actual bipolar output, you need the opamp level shifter/scaler.
  23. The Digilent proprietary USB UART/JTAG circuity allows for simultaneous jtag and uart use.The board appears as two serial ports. Vivado and the SDK automatically find the jtag port and you can use a communication app like TeraTerm using the other port. The "hello world" example you can create in the SDK demonstrate that. Serial communication with the pc is fairly common.
  24. The Arty board has all the JTAG circuitry plus a USB UART on board. You don't need a special cable - just use a good quality USB to micro USB cable. In the Vivado IPI, when you instantiate a Microblaze core, the MDM is automatically added and connected by block automation. The Xilinx SDK debugger will automatically use the MDM for debugging. You don't have to do anything other than start your program in debug mode. It sounds to me like going through one of the numerous online tutorials would help you get your bearings. Digilent has several including this one.Prolific blogger Adam Taylor also starts a series of posts on the Arty here. And if you like watching videos, Jeff Johnson at FPGADeveloper.com has this one.
  25. For those interested, Xilinx has just made a new Zynq MPSoC ebook available here.