kwilber

Members
  • Content Count

    107
  • Joined

  • Last visited

  • Days Won

    8

Everything posted by kwilber

  1. Xilinx had a thread a few years ago that discussed this. They describe how you can get by without a level shifter. There is also an old Digilent forum thread that discusses a similar project using a Basys3.
  2. According to the HCSR04 datasheet, it requires 5v for Vcc. The zybo reference manual shows, in section 16, pmods only have 3.3 v on pins 6 and 12. You would need a level shifter and a 5v supply powering the HCSR04.
  3. This core and this core are pretty easy to use and do not require a microblaze or zynq. Zynq based boards typically have the PHY connected to the PS. This makes it a bit difficult to use the PHY from the PL. There is a Xilinx wiki that describes accessing the PHY from the PL.
  4. You can find an example of driving the Cora RGB leds here. The demo has the rgb leds as ports on the top level design and uses simple logic to control them. If you want to control them from the PS, you could use an AXI GPIO block or an AXI PWM block.
  5. The example project you referenced is for a different manufacturers board (the Blackboard) and they have an rgb led on the mio bank. The Cora schematic you linked shows the rgb leds are on bank 35 on sheet 8.
  6. You downloaded the zip for the repo. The .xpr file is specific to the version of vivado used to create a project. Since the repo can be used with different versions of Vivado, an.xpr file is not provided. You need to use the Release zip from the Releases page. Note that you must use the version of Vivado that matches the release zip. Complete instructions for running the demo are given in the "Demo Setup" section of the README.md file.
  7. Just curious, does the elf file you are trying to load use interrupts? The second link explains how the large gap between the interrupt vector table and the start of the program results in huge file sizes.
  8. Here are two additional articles I have read on the technique being applied to a zynq. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842065/Zynq-7000+AP+SoC+Low+Power+Techniques+part+5+-+Linux+Application+Control+of+Processing+System+-+Frequency+Scaling+More+Tech+Tip https://github.com/tulipp-eu/tulipp-guidelines/wiki/Dynamic-voltage-and-frequency-scaling-(DVFS)-on-ZC702
  9. Is this a simple a-b vs b-a thing? Addition is commutative sub subtraction is not.
  10. I have previously used this tutorial and did not experience 2 minute boot times. Perhaps you could run through the tutorial and see how it behaves on your board. There was also an old Xilinx answer record about eliminating large gaps in the s-record file. The steps outlined in there might help.
  11. Vivado is complaining that there are active (not commented) pins in the constraint file that do not have matching port names in your design. Open your design_1_wrapper.v file and reconcile the port names specified there with the constraints file. It is not uncommon to have to change the name of a pin in the constraints file to match the port name in the wrapper. This could happen for example if you used "Make external" on an i/o pin from an IP block. One thing that has helped in the past was to delete the top level wrapper and regenerate it. Sometimes when you make pins external after generating the wrapper, there can be inconsistencies between port and pin naming. Xilinx UG903, page 42 and following elaborates on the scoping mechanism Vivado uses.
  12. When you installed Vivado, did you include support for Artix7 devices? You can check using the "Add Design Tools or Devices" command in the help menu. I apologize that I can not paste screen snips, but I have reached the limit the forum allows for my attachments.
  13. Have you set up the Arty and Olimex ARM-USB-TINY-H as detailed in chapter 2 of this document? It looks like the TINY-H connects to the Arty via pmod JD.
  14. One of the things those new to Xilinx struggle with is the terminology. I think this thread is a good example of that. The OP was thinking in terms like schematic and symbol whereas the Xilinx concepts are block design, IP, packaging and rtl module. While @zygot is correct that DocNav is the ultimate reference, I found my DocNav searches became more effective as I became more familiar with Xilinx terminology.
  15. A couple Xilinx quick take videos to give you an overview. https://www.xilinx.com/video/hardware/referencing-rtl-modules-for-vivado-ip-integrator.html https://www.xilinx.com/video/hardware/packaging-custom-ip-integrator.html The IP packager user guide https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1118-vivado-creating-packaging-custom-ip.pdf And chapter 12 in the IPI guide https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug994-vivado-ip-subsystems.pdf
  16. This article series evaluated the lowRisc and SiFive cores. I went through the lowRisc getting started guide on my Nexus A7 and it worked as advertised.
  17. @Ahmed Alfadhel, One other thing to note is your scope was AC coupled in your pictures so you were "seeing" a bipolar waveform of -1.28v to +1.28v. If you had DC coupled, the waveform on the scope would have shifted up and you would have observed the 0v to 2.5v the DA was outputting. To get an actual bipolar output, you need the opamp level shifter/scaler.
  18. The Digilent proprietary USB UART/JTAG circuity allows for simultaneous jtag and uart use.The board appears as two serial ports. Vivado and the SDK automatically find the jtag port and you can use a communication app like TeraTerm using the other port. The "hello world" example you can create in the SDK demonstrate that. Serial communication with the pc is fairly common.
  19. The Arty board has all the JTAG circuitry plus a USB UART on board. You don't need a special cable - just use a good quality USB to micro USB cable. In the Vivado IPI, when you instantiate a Microblaze core, the MDM is automatically added and connected by block automation. The Xilinx SDK debugger will automatically use the MDM for debugging. You don't have to do anything other than start your program in debug mode. It sounds to me like going through one of the numerous online tutorials would help you get your bearings. Digilent has several including this one.Prolific blogger Adam Taylor also starts a series of posts on the Arty here. And if you like watching videos, Jeff Johnson at FPGADeveloper.com has this one.
  20. For those interested, Xilinx has just made a new Zynq MPSoC ebook available here.
  21. The uart and jtag circuitry is proprietary and in not shown in the schematics for most of the Digilent boards.
  22. For readers not familiar with why C0G is better than X5R in this application, you can find a simple explanation here. (The links @MagicianT posted above go into much more detail.) In particular it explains (C0G have class 1 dielectrics. X5R have class 2 dielectrics)... "If you design audio devices, or if you simply prefer quiet PCBs, you have another reason to choose C0G over X7R or X5R: Class 2 caps exhibit piezoelectric behavior that can cause them to function as both microphones (that will convert sound into electrical noise) and buzzers (that will convert AC signals into audible noise). Class 1 capacitors don’t have this problem."
  23. Also, you should be able to use the Xilinx Licensing site to move a license.
  24. kwilber

    NEXSYS 4 DDR XADC DEMO

    You need to download the zip from the Releases page. I currently see packages for Vivado 2016.4 and 2018.2. The demo projects should be used with the specified version of vivado.
  25. kwilber

    TCS34725 Basys3 VHDL

    To make sure I was not misleading you, I just put together a project for the Arty using a PmodCOLOR using the technique I described. In addition to the PmodCOLOR block, AXI gpio block and microblaze block, I added an AXI Uart block so rgb values could be dumped to a terminal. You should be able to assemble the blocks on your basys 3. The procedure to build a microblaze based design in vivado can be found here. Follow the microblaze path. I used the PmodCOLOR demo app as a starting point and extended it to use the AXI gpio to set two leds. If you have the digilent IP library installed, you can find the demo app in <vivado-library-install-location>\ip\Pmods\PmodCOLOR_v1_0\drivers\PmodCOLOR_v1_0\examples\main.c The main loop of the app looks like this. Most of the code is provided in the demo. I added the lines dealing with the leds. There is more to accurately determining color given rgb values, but my simple use of thresholds should suffice for this simple project. void DemoRun() { u8 ID; u32 leds; COLOR_Data data; CalibrationData calib; xil_printf("Pmod COLOR Demo launched\r\n"); ID = COLOR_GetID(&myDevice); xil_printf("Device ID = %02x\r\n", ID); // Turn on sensor led to illuminate objects passed over the sensor COLOR_SetLED(&myDevice,1); data = COLOR_GetData(&myDevice); calib = DemoInitCalibrationData(data); usleep(2400); while (1) { data = COLOR_GetData(&myDevice); DemoCalibrate(data, &calib); data = DemoNormalizeToCalibration(data, calib); xil_printf("r=%04x g=%04x b=%04x\n\r", data.r, data.g, data.b); // Thresholds empirically chosen. // Led1 lights for red object // Led2 lights for green object leds = data.r > 0x8000 ? 0x01 : 0; leds |= data.g > 0x5000 ? 0x02 : 0; XGpio_DiscreteWrite(&myLeds, 1, leds); usleep(500000); } } Running the app and moving a red object over the sensor produced output similar to this: Pmod COLOR Demo launched Device ID = 44 r=0000 g=0000 b=0000 r=0000 g=0000 b=0000 r=0000 g=0000 b=0000 r=0000 g=0000 b=0000 r=0073 g=0026 b=0022 r=0073 g=0026 b=0022 r=0073 g=0026 b=0022 r=0073 g=0026 b=0022 r=384C g=0C3F b=0BFD r=A84E g=28B0 b=25A1 r=A6B1 g=27EE b=253F r=A69B g=27F4 b=2544 r=A69B g=27F4 b=2544 r=A69B g=27F4 b=2544 r=9020 g=2339 b=208C r=9020 g=2339 b=208C r=0004 g=0003 b=0002 r=0004 g=0003 b=0002