kwilber

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  1. You need to install the digilent board files. The procedure is detailed in section three of this wiki page.
  2. The error message is not very obvious. In the guide it says "If it doesn’t say Bus Width: 4-bit, then your SD-Card failed to be detected or was stuck in an incorrect mode. You should hit the CPU_RESET and/or power off to retry"
  3. The bit file in QSPI only implements the system hardware and a simple first stage bootloader. Very similar to how pc's have a bootloader in rom but load the actual operating system from disk. The SD card will hold the actual linux file system and is just like a disk drive in your pc. There are 4 partitions on the card. First, there is a FAT32 partition that has boot.bin. This is a more capable loader that knows about the structure of the sd card and can locate and read the linux kernel. A second ext4 formatted partition holds the kernel. A third partition is for s
  4. Hello @aeon20 I replied to your PM but will also reply here so others can benefit. I followed the getting started guide and used the "standalone installation" option. On my Nexys A7 100T, I made sure sw1 was on and the others were off. JP1 was set to QSPI and JP2 was set to USB. I attached a usb keyboard and vga monitor. I initially left the sd card out so I could observe the behavior. The read from the sd failed as expected. The quickstart mentions that a reported bus width other than 4 bytes is an error. 0: 0 1: 1 2: 1 3: 1 800: 1e 801: 0 802: 0 803: 0 Selftest iteration
  5. This link explains why the xadc is being included when you use the mig. https://www.xilinx.com/support/answers/51687.html
  6. Xilinx had a thread a few years ago that discussed this. They describe how you can get by without a level shifter. There is also an old Digilent forum thread that discusses a similar project using a Basys3.
  7. According to the HCSR04 datasheet, it requires 5v for Vcc. The zybo reference manual shows, in section 16, pmods only have 3.3 v on pins 6 and 12. You would need a level shifter and a 5v supply powering the HCSR04.
  8. This core and this core are pretty easy to use and do not require a microblaze or zynq. Zynq based boards typically have the PHY connected to the PS. This makes it a bit difficult to use the PHY from the PL. There is a Xilinx wiki that describes accessing the PHY from the PL.
  9. You can find an example of driving the Cora RGB leds here. The demo has the rgb leds as ports on the top level design and uses simple logic to control them. If you want to control them from the PS, you could use an AXI GPIO block or an AXI PWM block.
  10. The example project you referenced is for a different manufacturers board (the Blackboard) and they have an rgb led on the mio bank. The Cora schematic you linked shows the rgb leds are on bank 35 on sheet 8.
  11. You downloaded the zip for the repo. The .xpr file is specific to the version of vivado used to create a project. Since the repo can be used with different versions of Vivado, an.xpr file is not provided. You need to use the Release zip from the Releases page. Note that you must use the version of Vivado that matches the release zip. Complete instructions for running the demo are given in the "Demo Setup" section of the README.md file.
  12. Just curious, does the elf file you are trying to load use interrupts? The second link explains how the large gap between the interrupt vector table and the start of the program results in huge file sizes.
  13. Here are two additional articles I have read on the technique being applied to a zynq. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842065/Zynq-7000+AP+SoC+Low+Power+Techniques+part+5+-+Linux+Application+Control+of+Processing+System+-+Frequency+Scaling+More+Tech+Tip https://github.com/tulipp-eu/tulipp-guidelines/wiki/Dynamic-voltage-and-frequency-scaling-(DVFS)-on-ZC702
  14. Is this a simple a-b vs b-a thing? Addition is commutative sub subtraction is not.
  15. I have previously used this tutorial and did not experience 2 minute boot times. Perhaps you could run through the tutorial and see how it behaves on your board. There was also an old Xilinx answer record about eliminating large gaps in the s-record file. The steps outlined in there might help.