kwilber

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kwilber last won the day on March 23

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  1. This core and this core are pretty easy to use and do not require a microblaze or zynq. Zynq based boards typically have the PHY connected to the PS. This makes it a bit difficult to use the PHY from the PL. There is a Xilinx wiki that describes accessing the PHY from the PL.
  2. You can find an example of driving the Cora RGB leds here. The demo has the rgb leds as ports on the top level design and uses simple logic to control them. If you want to control them from the PS, you could use an AXI GPIO block or an AXI PWM block.
  3. The example project you referenced is for a different manufacturers board (the Blackboard) and they have an rgb led on the mio bank. The Cora schematic you linked shows the rgb leds are on bank 35 on sheet 8.
  4. You downloaded the zip for the repo. The .xpr file is specific to the version of vivado used to create a project. Since the repo can be used with different versions of Vivado, an.xpr file is not provided. You need to use the Release zip from the Releases page. Note that you must use the version of Vivado that matches the release zip. Complete instructions for running the demo are given in the "Demo Setup" section of the README.md file.
  5. Just curious, does the elf file you are trying to load use interrupts? The second link explains how the large gap between the interrupt vector table and the start of the program results in huge file sizes.
  6. Here are two additional articles I have read on the technique being applied to a zynq. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842065/Zynq-7000+AP+SoC+Low+Power+Techniques+part+5+-+Linux+Application+Control+of+Processing+System+-+Frequency+Scaling+More+Tech+Tip https://github.com/tulipp-eu/tulipp-guidelines/wiki/Dynamic-voltage-and-frequency-scaling-(DVFS)-on-ZC702
  7. Is this a simple a-b vs b-a thing? Addition is commutative sub subtraction is not.
  8. I have previously used this tutorial and did not experience 2 minute boot times. Perhaps you could run through the tutorial and see how it behaves on your board. There was also an old Xilinx answer record about eliminating large gaps in the s-record file. The steps outlined in there might help.
  9. Vivado is complaining that there are active (not commented) pins in the constraint file that do not have matching port names in your design. Open your design_1_wrapper.v file and reconcile the port names specified there with the constraints file. It is not uncommon to have to change the name of a pin in the constraints file to match the port name in the wrapper. This could happen for example if you used "Make external" on an i/o pin from an IP block. One thing that has helped in the past was to delete the top level wrapper and regenerate it. Sometimes when you make pins external after generating the wrapper, there can be inconsistencies between port and pin naming. Xilinx UG903, page 42 and following elaborates on the scoping mechanism Vivado uses.
  10. When you installed Vivado, did you include support for Artix7 devices? You can check using the "Add Design Tools or Devices" command in the help menu. I apologize that I can not paste screen snips, but I have reached the limit the forum allows for my attachments.
  11. Have you set up the Arty and Olimex ARM-USB-TINY-H as detailed in chapter 2 of this document? It looks like the TINY-H connects to the Arty via pmod JD.
  12. One of the things those new to Xilinx struggle with is the terminology. I think this thread is a good example of that. The OP was thinking in terms like schematic and symbol whereas the Xilinx concepts are block design, IP, packaging and rtl module. While @zygot is correct that DocNav is the ultimate reference, I found my DocNav searches became more effective as I became more familiar with Xilinx terminology.
  13. A couple Xilinx quick take videos to give you an overview. https://www.xilinx.com/video/hardware/referencing-rtl-modules-for-vivado-ip-integrator.html https://www.xilinx.com/video/hardware/packaging-custom-ip-integrator.html The IP packager user guide https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1118-vivado-creating-packaging-custom-ip.pdf And chapter 12 in the IPI guide https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug994-vivado-ip-subsystems.pdf
  14. This article series evaluated the lowRisc and SiFive cores. I went through the lowRisc getting started guide on my Nexus A7 and it worked as advertised.
  15. @Ahmed Alfadhel, One other thing to note is your scope was AC coupled in your pictures so you were "seeing" a bipolar waveform of -1.28v to +1.28v. If you had DC coupled, the waveform on the scope would have shifted up and you would have observed the 0v to 2.5v the DA was outputting. To get an actual bipolar output, you need the opamp level shifter/scaler.