• Content Count

  • Joined

  • Last visited

About kwilber

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. kwilber

    pmod wifi

    @harika, When I download the zip file, I see a complete archived Vivado project as shown below. Perhaps the zip file you tried to open was incomplete or corrupted? Once you have an intact zip file, you will need to extract the ZED_WIFI_SD directory from the zip file to some location on your system and then open the ZED_WIFI_SD.xpr file in Vivado 2017.4. I extracted the project to my local folder named "D:\zedboard\ZED_WIFI_SD". Doing that, you should see something like this.
  2. kwilber

    ERROR: cannot open block design

    The project you referenced was created in Vivado 2017.4. You can see that by looking at line 2 in the project file as shown here. You are trying to open it with Vivado 2016.2. More complex IP blocks, like the Xilinx vdma block referenced in the error message, are typically dependent on the version of Vivado used to create the project. While it is usually possible to upgrade a project from an earlier version of Vivado to a newer version, going from a newer version back to an older version almost never works with anything but simple projects. You should install Vivado 2017.4 and use that to work with the project. Xilinx has done a good job making sure different versions of Vivado can coexist on the same workstation, provided you have the disk space. So you would not need to uninstall Vivado 2016.2.
  3. kwilber

    Generate .mcs file without Vivado

    Quoting from the FPGA Cores website "Currently we support Xilinx 7 Series (Artix, Kintex, Zynq and Virtex)". That being said, to use the IP, the board has to have the required components, eg a serial flash and an Ethernet PHY with either a MII or RMII interface to the MAC. I would again suggest you contact FPGA Cores directly.
  4. kwilber

    Generate .mcs file without Vivado

    The FPGA Cores solution does program the flash, but I have only used it to program single images into the Arty's Quad-SPI flash. Multiboot may be beyond scope of the FPGA Cores solution as listed on their website. You would have to contact FPGA Cores directly to inquire about multiboot capability.
  5. kwilber

    Generate .mcs file without Vivado

    The website FPGA Cores has IP that allows remote programming of .bin files over ethernet that I have used on my Arty. It might be worth a look.
  6. kwilber

    Pmod on Arduino

    I had noted in my reply that the PmodLVLSHFT is not convenient to use for other Pmods. It is better suited for jtag and fly-wire use. What I was talking about was a "flow through design" being able to plug an existing Pmod onto one end of the shifter and plug the other end of the shifter into your controller's Pmod port. I have done this using either the TXB0108 previously mentioned as well as a TXS0108 which is more suitable for I2C use.
  7. kwilber

    Pmod on Arduino

    Hello @JColvin, I would imagine a Pmod logic level shifter with a flow through path would make a good addition to the Pmod line up. The existing Pmod LVLSHFT is not convenient when used with other Pmods. I used a Pmod BB with a TXB0108 ( to create my own "Pmod Shift". It makes it very easy to use 3.3v Pmods with an Arduino.
  8. kwilber

    Nexys 4 DDR Blinky tutorial error generating Bitstream

    I am glad that helped. Digilent's tutorials and sample projects are great. Just keep in mind that they are developed for a specific board using a specific version of Vivado, so you have to be on the lookout for things you have to tweak when porting to a different board/device or Vivado version. This also applies to many open source projects you find on the web.
  9. kwilber

    Nexys 4 DDR Blinky tutorial error generating Bitstream

    Remember that Verilog is case sensitive and this extends to names in the constraints file. Your blinky.v source file uses "led" (lower case). The constraints file uses "LED" (upper case). I also noticed that the constraints file you attached names the clock as "CLK100MHZ" but your blinky.v refers to it as "clk". If you reconcile the names between blinky.v and Nexys-4-DDR-Master.xdc, you should be able to generate a bitstream. I implemented blinky with my Arty A7-35 as shown below. Note I created the constraints file blinky.xdc and copied only the relevant clock and led lines from the master constraints file to make it easier to see. Also note the pin locations shown for my Arty board will be different from the pin locations for your Nexys board.
  10. The board pictured is an original Zybo, not a Zybo Z7-10. The most obvious way to tell is the Zybo has a vga port. The Zybo Z7-10 and Zybo Z7-20 have two hdmi ports. If you in fact have a Zybo and not a Zybo Z7-10, I recommend redoing the the tutorial from the beginning and this time select the Zybo in step 1.6.
  11. The system clock does not need to be connected. Did you make sure to select "Include bitstream" in step 7 where you exported the hardware to the SDK? Does the "Done" led on the board illuminate after programming the FPGA in step 11.1? Did you select "Run as..." or "Debug as..." in step 11.3? If you selected "Debug as..." the system maybe be sitting at a breakpoint at the start of your application. If you had selected "Debug as..." and are sitting at a breakpoint, the SDK would have prompted you that it was switching to debug perspective and you would see something like this. Nothing would function until you told it to "continue" by either hitting F8 or clicking the icon in the toolbar.
  12. Did you install the Digilent board files as described in the prerequisites section of the tutorial? They can be found here. If not, and you tried to follow the tutorial exactly, you may have selected the older Zybo board which has some differences as described here. In step 1.6 of the Getting Started tutorial, make sure you select the Zybo Z7-10 and not the Zybo as shown in this snip. If you have correctly specified the board, it should be reflected in the Project Summary that you see when the Project Manager node is selected in the Flow Navigator as shown below.
  13. kwilber

    Arty Z7 echo server

    In the Vivado File menu, there is an "Archive Project ..." command. That will create a zip file with the current state of your project.
  14. kwilber

    Arty-Z7 20: HDMI pass-through project black screen

    I re-targeted my design for the Arty-Z7 and upgraded the project to Vivado 2017.4. I can verify the design functions. The image below shows the GoPro focused on the Arty and the image displayed on the monitor. It takes the GoPro maybe 15 seconds once you plug in the hdmi cable before it starts outputting the image. Let me know if you want me to upload the project archive.
  15. kwilber

    Arty-Z7 20: HDMI pass-through project black screen

    I have a similar project done with Vivado 2016.4 working on a Zybo Z7. You might try adding a Hot Plug Detect as shown in my block design. The constant block value is set to 1. My design was connected to a GoPro4 set to 720p so my rgb2dvi used <80Mhz (720p) and rgb2dvi was set to 1280x720 and <120Mhz. My clk_in1 and clk_out1 were the same as yours.