kwilber

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kwilber last won the day on March 20

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  1. kwilber

    Pmod DA3 clocking

    My project wrote to the dac about every 4 usec. To write 2 ^ 16 = 65536 values, it took about 262 msec per cycle, which gives a frequency close to 3.81 hz. I conservatively used ext_spi_clk = 25 Mhz so my sclk rate was 12.5 Mhz. In the zoomed trace, you can see 16 bits took about 1.28 usec to clock into the pmod. I had ~CS go valid about 1.25 usec before I started writing the bits and kept it valid for about 1.25 usec after the bits were clocked out. The rest of the time was from loop overhead. You appear to be writing almost 70 times faster. Your waveform is not as smooth as mine, so I would guess you are writing so fast the dac is missing some of your data points. Are you using the version of xspi.c from my example project?
  2. kwilber

    Pmod DA3 clocking

    Inside the AD5541A, the MOSI bits get clocked into a shift register and are held there until the ~CS line goes high. At that time, the bits are transferred from the shift register to the D/A. It does not matter what level is on MOSI at that instant. In the traces I posted earlier, I included a transition from full scale output to 0. I also show several cycles of writing all possible values in a ramp. The resulting voltage waveform shows the AD5541A is seeing the data correctly. The last four writes to the pmod in the zoomed trace show sending the values 0, 1, 2 and 3 to the D/A. You can observe SCLK's transition in relation to the least significant bits of the data. SCLK is not transitioning when ~CS transitions to high so the data on MOSI is "don't care" at that instant. I did use different clocks since the microblaze can run at higher clock rates than the AD5541A. Also, when you are troubleshooting, it can sometimes help to slow down the logic. I see you are using pmod connector JB whereas my project used JA. Just as a test, you might want to try moving your PmodDA3 to JA and use my project as is to replicate my results. You should be able to launch vivado, open my project then immediately launch the SDK from vivado. You should not have to generate a bitfile. I had included the hardware handoff in the zip file I gave you so you have my exact bitfile. Once the SDK loads, it should automatically load the project and compile it. At that point you can program the fpga from inside the SDK and then run my example app. You should see a sawtooth waveform coming out of the PmodDA3 if all is well.
  3. kwilber

    Pmod DA3 clocking

    I included visualizations of the ~CS, SCLK and DIN lines in the logic analyzer trace I posted Tuesday at 2:51 AM. In the trace, MOSI is the DIN line, Enable is the ~CS line and Clock is the SCLK line. Did the Xilinx SDK report any errors while opening the workspace? Did you program the fpga from the SDK?
  4. kwilber

    NEXYS 3 frequency meter

    The problem is likely in the .ucf file where you define pin information. The error message says device pin LL8 doesn't exist. If you post the contents of your ucf, we can probably figure it out.
  5. kwilber

    FMC Breakout

    I like the IAM electronics board better because you can stack another board on top, somewhat like a pcie card interposer. The Xilinx XM105 is ok but I had to use ribbon cables to get the signals to a prototyping board. That may not be a problem if you are routing lower speed signals thru the FMC, but it might affect the fidelity of higher speed signals.
  6. kwilber

    FMC Breakout

    Something like these? https://www.tindie.com/products/IAM_ELECTRONIC/fpga-mezzanine-card-fmc-breakout-board http://www.kayainstruments.com/fmc-prototype-board/
  7. kwilber

    CMOD a7-35t Schematic

    I found this page useful. About 1/3 the way down is a picture of the two boards side by side.
  8. Ah thats right, I had to correct that as well. Just change the instance name of the up/down counter to counter. Sorry I forgot about that. up_down_counter counter ( .clk(clk_div), .counter(counter1) );
  9. The simulation ran without issue for me. The error message indicates there were errors during the compile. Can you post the full output? After you took care of the "non-module files", did you use the "Refresh hierarchy" command (right click in the sources window and select "Refresh hierarchy"). Did you retarget the project for the Zedboard? (double click on the "Project part" link in the "Project Summary").
  10. You can delete the reference to DA2RefComp.vhd under non-module files (right click on the file and select "Remove file from project"). Then re-add the file to the project using the "Add sources" command. Simply copying the file to the directory from outside of vivado is not sufficient for vivado to know about the file.
  11. kwilber

    CMOD a7-35t Schematic

    The cmod resource page has the schematic here.
  12. kwilber

    Pmod DA3 clocking

    @Ahmed Alfadhel, I have sent you a PM with a link to the project archive. The forum limits the size of attachments so I am not able to upload it.
  13. kwilber

    Pmod DA3 clocking

    I forgot you were using an Arty. I will retarget my project to use an Arty A35 and will then post it.
  14. kwilber

    Pmod DA3 clocking

    I obtained a DA3 and was able to get it working. Here are some pictures of my setup. I am limited by how big the attachments are so I will post again with an archive of the project I used.
  15. Hello @mehmetdemirtas89, Yes, you can use the PmodDA2 with the zedboard. Note that there is no IP core in Digilent's vivado_library for the DA2. However, on the reference page for the DA2, you can find usage information. You can download the verilog example and the reference component. You will need to retarget the example project to use the zedboard instead of an Artix based board. You will also have to supply a constraints file for the project. Here is the physical setup I tested. (My zedboad's jtag usb connector broke off a while back so I have to use the Xilinx platform cable to program) Here is what the logic analyzer shows while it is running And zoomed so you can see the writes