I have just bought the Nexys Video Artix-7 FPGA development board and would like to run the audio demo. I followed the instructions provided here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-dma-audio-demo/start
but the project does not run. I understand that this demo was created for an older version of Vivado and there will be some version issues. I was able to update the library functions and the TCL script as described here: https://forum.digilentinc.com/topic/4787-hdmi-output-demo-top-module/?page=0#comment-19393
but, I still can't run the simulation or generate the bitstream, get the following error:
[Common 17-70] Application Exception: Top module not set for fileset 'sources_1'. Please ensure that a valid value is provided for 'top'. The value for 'top' can be set/changed using the 'Top Module Name' field under 'Project Settings', or using the 'set_property top' Tcl command (e.g. set_property top <name> [current_fileset]).
It seems that there is no entry function to the design. How can I fix this?
Also, I would like to look at synthesizing the audio C code. Does the example project include C synthesis?