Hi, I learnt Verilog on my own and haven't touched about the logic design for many years. The schematic capture let you know about the idea of gate design. However, most of the digital design projects need HDL skillsets.
I think once you understand the digital design theory. You can catch up the Verilog / VHDL.
Digilent has a learn module learn.digilentinc.com to teach people how to use Vivado to learn Verilog.
First of all: you won't be able to use Vivado with Spartan 3 FPGA (which is present on Nexys2). Therefore moving towards Artix 7 FPGAs seems to be a good decision.
1. Indeed, Vivado does not convert schematic sources
But you can do something else.
In ISE, under "Design Utilities", you can find "View HDL Functional Model" which shows you the VHDL or Verilog code corresponding to your schematic. The language VHDL or Verilog is chosen according to the setting "Preferred Language" in "Design Properties" of your project.
For VHDL for example, you will see a file having vhf extension. In order to have a VHDL source file (vhd extension), you should rename the file to vhd extension, remove schematic source file and add vhd file. Like this you will replace the schematic sources with HDL sources.
2. I consider that learning to use VIvado is a smart decision as XIlinx seems to push forward this new tool. So this might be the future. Using Vivado is somehow different than ISE but is not much more complicated. And there are also things that might be regarded as simpler (you do the programming in Vivado, for example).
3. There are no explicit prerequisites. Of course you should understand what is a HDL (Hardware Description Language) but this understanding will come while working with VHDL or Vivado.
Good luck, and write us if you have further questions.