Sandeep I

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  1. Can we declare Generate if-for statement? module prac#(parameter m=3) (input x, input[2:0]a,b,output[2:0]c); wire [2:0]f[0:3]; genvar i; generate if(!x) begin : d2 for(i=0;i<=m;i=i+1) begin:dd assign f=(a & b); end end endgenerate endmodule It is saying that 'x' is not a constant. Thanks in advance.
  2. Thanks @jpeyron. I did a few mistakes in declaration. I have declared a as register and I used continuous statement and in continuous statement we can't declare a where i is not a constant.
  3. I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet: module coedata(clk,rst,a); input clk,rst; output [31:0]a; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out); // just gives count in 'out' to access address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0]