# tnet

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1. ## Artix-A7 CMOD I/O Pins - Need more I/O Pins

Board: https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start (Artix CMOD A7-35T). This board comes with 48 I/O pins only. Is this board able to handle some extension board connector to allow me to use more I/O pins (~ 84 Digital I/O Pins)? If so, please state the name. Is there any other method you know of? Thank You. Update: This board has 1 PMOD connector with 8 Digital I/O). Can I not use a PMOD IOXP: I/O Expansion Board to handle 19 I/O? Let me know. PMOD IOXP: https://store.digilentinc.com/pmod-ioxp-i-o-expansion-module/
2. ## Systematic approach for Verilog implementation

Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs a
3. ## Verilog Question

Looking at this link: http://referencedesigner.com/tutorials/verilogexamples/verilog_ex_04.php Essentially, this code does clock conversion. Why is this tutorial setting the WIDTH to be 3 and N=6? In their example, they say if I want to convert a 50 MHz clk to 5 Mhz, set N = 5. But why? What is the math/logic behind this so I can understand it. The width (3), is the register size. Therefore it's 2^3 and can address up to 8 bits. That part makes sense. Let me know.
4. ## Artix-A7 (CMOD-A7) System Clock Question

Hi @[email protected], the code below shown in your clocking management. The DCM_SP and ".CLKDV_DIVIDE, .CLKFX_, etc..." are usable in the Artix-A7 Cmod-A7 35T? I didn't see these in the datasheet, so wasn't sure if I'm able to define these. // // Clock management // // Generate a usable clock for the rest of the board to run at. // wire ck_zero_0, clk_s, clk_sn; // Clock frequency = (20 / 2) * 8Mhz = 80 MHz // Clock period = 12.5 ns DCM_SP #( .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(2), // Here's the divide by two .CLKFX_MULTIPLY(20), // and here's the multiply by 20 .CLKIN_DIVIDE_B
5. ## Artix-A7 (CMOD-A7) System Clock Question

Hi, Thanks for the reply. Regarding the clocking wizard to to output an 8MHz freq. Is this clocking wizard within Vivado I'm assuming? If so, then that makes sense. What about if I'm purely testing this on ModelSim, therefore there is no clocking wizard and it would be purely down in verilog, no? Is there a mathematical way I can see this being shown, that tells me type bit-counter to use, etc, and replicating it in verilog. Other than that, this makes sense. Thanks.
6. ## Artix-A7 (CMOD-A7) System Clock Question

Regarding the the board Artix-7 (CMOD-A7) - https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.