tnet

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  1. Board: https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/start (Artix CMOD A7-35T). This board comes with 48 I/O pins only. Is this board able to handle some extension board connector to allow me to use more I/O pins (~ 84 Digital I/O Pins)? If so, please state the name. Is there any other method you know of? Thank You. Update: This board has 1 PMOD connector with 8 Digital I/O). Can I not use a PMOD IOXP: I/O Expansion Board to handle 19 I/O? Let me know. PMOD IOXP: https://store.digilentinc.com/pmod-ioxp-i-o-expansion-module/
  2. Hello, As I am a novice to Verilog/SystemVerilog, I am seeking for some guidance regarding writing Verilog logic from purely just a timing diagram. (You may have seen my other posts). For example, if my goal is to implement a logical block that has X inputs and Y outputs for the DUT, and all I am given is a timing diagram that shows the behavior of the input and output signals and how they behave according to the supplied clock. What is the best way to tackle this problem from an engineering perspective? Should I be considering to first simply layout the module with the inputs and outputs and see how the timing diagram behaves and try to implement the logic based off of that? Or should I be first be treating this as a "state machine" and draw a systematic schematic of showing all the inputs and outputs, showing when they should go HIGH or LOW at their certain times? Are timing diagrams usually implemented in a state machine logical flow? Was hoping to gain some knowledge and understanding from the people who are experienced writing Verilog logic based off of timing diagrams and was hoping to see your systematic approach of how it should be implemented as if I was an engineer. Thank You.
  3. tnet

    Verilog Question

    Looking at this link: http://referencedesigner.com/tutorials/verilogexamples/verilog_ex_04.php Essentially, this code does clock conversion. Why is this tutorial setting the WIDTH to be 3 and N=6? In their example, they say if I want to convert a 50 MHz clk to 5 Mhz, set N = 5. But why? What is the math/logic behind this so I can understand it. The width (3), is the register size. Therefore it's 2^3 and can address up to 8 bits. That part makes sense. Let me know.
  4. Hi @D@n, the code below shown in your clocking management. The DCM_SP and ".CLKDV_DIVIDE, .CLKFX_, etc..." are usable in the Artix-A7 Cmod-A7 35T? I didn't see these in the datasheet, so wasn't sure if I'm able to define these. // // Clock management // // Generate a usable clock for the rest of the board to run at. // wire ck_zero_0, clk_s, clk_sn; // Clock frequency = (20 / 2) * 8Mhz = 80 MHz // Clock period = 12.5 ns DCM_SP #( .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(2), // Here's the divide by two .CLKFX_MULTIPLY(20), // and here's the multiply by 20 .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(125.0), .CLKOUT_PHASE_SHIFT("NONE"), .CLK_FEEDBACK("1X"), .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"), .PHASE_SHIFT(0), .STARTUP_WAIT("TRUE") ) u0( .CLKIN(i_clk_8mhz), .CLK0(ck_zero_0), .CLKFB(ck_zero_0), .CLKFX(clk_s), .CLKFX180(clk_sn), .PSEN(1'b0), .RST(1'b0));
  5. Hi, Thanks for the reply. Regarding the clocking wizard to to output an 8MHz freq. Is this clocking wizard within Vivado I'm assuming? If so, then that makes sense. What about if I'm purely testing this on ModelSim, therefore there is no clocking wizard and it would be purely down in verilog, no? Is there a mathematical way I can see this being shown, that tells me type bit-counter to use, etc, and replicating it in verilog. Other than that, this makes sense. Thanks.
  6. Regarding the the board Artix-7 (CMOD-A7) - https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.
  7. @xc6lx45 I see the the G3/G2/H2/J2 in Bank 35 of the I2CD. Therefore, I have 4? Also, Looking at the datasheet you linked me above, there is this image in there shown below. It is showing that there are 16 External Analog Inputs. Therefore, I can physically just connect to ONE of the 2 analog pins on board since each pin is capable of addressing a 16-bit MUX? I forgot to mention, my input signals are 16-bit Long as well (CLK, 4-bit MUX, 9-bit Analog signals, and 2 other signals), total of 16. So does this not work?
  8. @xc6lx45 Disregarding my original question, looking purely at the CMOD A7. There are 2 Analog pins and the rest are digital I/Os. Therefore, I only have ADC 1 and ADC 2 on this board to physically connect to. What if I want to send in a MUX_ADC[3:0] as input to this FPGA? How does this connection work (Physically), is it implemented in the Verilog code? If there are only ADC pins, aren't they just 1-bit? Could you clear out this confusion.
  9. Hello, Specifications: Board: Artix-A7 35T (cpg236-1) FPGA Software: Vivado 2017.4 (Webpack) I am using the Vivado IP integrator and was looking at the IP Catalog. There is an XADC Wizard that allows us to implement an ADC block and or customize it to your needs. My question is, there is a circuit schematic I want to implement that uses an ADC. This circuit takes in multiple analog signals, CLK, etc, and outputs a BUS signal. Now, my confusion is, I am allowed to use this XADC wizard and generate an IP Core and manipulate it to my needs that it should behave as what is shown on my circuit schematic? The reason I am asking this is I am fairly new to Vivado and IP Integrator, therefore; rather than wasting time, I wanted to make sure if this is possible. Thank You.