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  1. I found a useful hint. When I assign my output port (to the AXIs bus) directly to och and och is updated on clk (100MHz) I can see the channel_out change. e.g. [email protected](posedge clk) begin och <= channel_out; end assign out_to_axis = och; but in the code in the previous post "out_to_axis" is assigned ofval. Interesting.
  2. Thanks @jpeyron I'm still having a bit of difficulty reading the output of the channel_out port correctly. I can see channel_out working correctly in the example code, but I have a custom AXI streaming IP that is managing the XADC but the method I am using always outputs zero. I'm not sure what I am doing wrong, since I am still using the ready signal as a trigger for saving the channel out to a register. For reference, this is how I am managing the XADC and channel out: //data & logic enable strobe generation [email protected](posedge clk) fork last_ready <= ready; join assign ready_pe_strobe = (last_ready == 1'b0 && ready == 1'b1) ? 1'b1 : 1'b0; assign ready_ne_strobe = (last_ready == 1'b1 && ready == 1'b0) ? 1'b1 : 1'b0; reg [4:0] och; reg [31:0] ofval; always @(posedge clk) begin if (ready_pe_strobe) och <= channel_out; if(EOS) begin if(Address_in == 7'h11) //A0: Tmon fork ADCsig = 3'b000; ofval <= {och,ADCsig,data}; datavalid <= 1'b1; join if(Address_in == 7'h19) //A1: HVmon fork //Address_in=7'h19; ADCsig = 3'b001; //A1: HVmon ofval <= {och,ADCsig,data}; datavalid <= 1'b1; join ... ... continues for 4 more channels end end best, Chris
  3. Thanks @jpeyron, Ah okay - I think I see what's going on. I attached the EOS signal to data_out on the example design and it looks like EOS going high does not correspond well with when channel_out is active. Is this the expected behaviour? The way I was reading the diagrams in UG480 on pages 72 and 75 is that the channel out would only be indeterminate briefly on the first cycle of the ADCCLK (e.g. immediately after busy goes low). Based on the example design I'm guessing the best time to grab the channel out would be on the drdy_out signal, does that make sense?
  4. I'm attempting to use all 6 single ended ADC channels of the PYNQ-Z1 board with DRP enabled and with continuous sequencing (see attached configuration). According to the 7-series XADC guide UG480 on page 72, "When XADC is being operated in a sequence mode, you can identify the channel being converted by monitoring the channel address (CHANNEL[4:0]) logic outputs. The multiplexer channel address of the channel being converted is updated on these logic outputs when BUSY transitions Low at the end of the conversion phase." But the output of the channel (channel_out) is always zero, which I've worked around by outputting the previously selected channel with the data on the EOS signal. The issue is that it seems some of my samples are being labeled incorrectly, for example with a 500Hz signal on A4 and a constant 0.23V on A2 this is what I get: As you can see, it looks like some of the sinusoidal signal is being labeled as A2 and some of the DC is being labeled as A4. It would be much easier to debug what was going on if I could just read the channel_out signal with the conversion on EOS, but for whatever reason it always reads zero when I connect a wire to channel_out. Is there anything else I have to configure to get this to work correctly? Thanks, Chris xadc_wiz_0.v
  5. Thanks @xc6lx45, Yes, I am aware of this. What's confusing to me is that when I attempt to use the DRP to select a single channel, several seem to all be active at at the same time.
  6. Hi again @jpeyron, So I'm still having weird issues with this board. I really need at least 3 active ADCs for my project, but at best I can only get 2 channels active (Vp/Vn and A0) without interference from other channels. Is there a mistake I'm making or is this board not working properly?
  7. Hi @jpeyron, So I've done a few more tests: 1) We have a second Arty z7-10, and I can confirm that the same behavior is happening with that board (all three differential channels seem to be active at the same time). 2) I ran the XADC demo on an Arty S7-50 and it behaved as expected, the switches would activate only one channel at a time. Could this be a bug with the XADC demo for the z7 or the channel sequencer? Additionally, I posted this question in Xilinx forums and got the suggestion of attaching the ila and looking at the output of the channels and eoc to see if there are any inconsistencies, so I am currently working on that.
  8. Thank you for your response jpeyron. I guess I'm a bit confused how to use the channel sequencer. When I use your code, it seems that the ADC responds to the differential channels Vp/Vn, A6/A7, and A8/A9 all simultaneously. What I am attempting to do is have one channel active (such as Vp/Vn), but then be able switch between Vp/Vn, A0 and A1 programmatically.
  9. Hi - I've been trying to implement a design based on the XADC demo for the Arty z7-10, but I've been having difficulty figuring out exactly how to properly switch between 3 channels (VP/VN, A0 and A1) when in DRP mode with the channel sequencer. I've attempted to use the switches to alternate channels as in the example design, though what I would ultimately like to do is poll each channel at a regular timed interval. Attached are my modifications to the example verilog source and XDC file, any help would be greatly appreciated. -Chris Artyz7_mod.xdc Artyz7_mod.v