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  1. @Bianca Thank you for this example project. All three boards show calibration success led with your pre-compiled .bit file. I checked differences from my project. I connected sys_clock directly to the MIG IP and updated MIG input clock Frequency settings to 100Mhz. Your project uses MCM to produce 200Mhz clock for MIG IP. I updated my project in the same way. Now I see calibration on all three boards with my project.
  2. Now we have three own boards with ISSI DDR. Before we also have two loaned boards with MIRA DDR. It was used to start developing process before receiving our order for Nexys 4 DDR boards.
  3. Hi @Bianca, Now we have three Nexys 4 DDR boards. All these three boards have the same DDR2 chip label: ISSI 1652 IS43DR16640C -25DBL K090 BNG137000V2 CHN But the new third board has working access to the DDR2 chip (calibration complete successfully) SN for these three boards: 1. DA6ECC0 - calibration complete successfully 2. DA6E850 - calibration fails 3. DA6E83F - calibration fails
  4. Hi Jon, It will be good if you can generate approved ".bit" file with connected any "DDR2 Calibrating Done" LED or some debug probes. I and @FPGA_LIFE can check it on our boards. It looks the best solution to exclude any our issues in Vivado synthesis workflow and to check the DDR2 chip calibration. * Currently official Nexys 4 DDR support page doesn't have any pre-compiled FPGA firmware to verify the DDR2 chip.
  5. We have 4 Nexys 4 DDR boards with the same "Rev C" revision. I have compiled .bit file with MIG IP settings based on Digilent example "Nexys 4 DDR Xilinx MIG Project" in Vivado 2018.1 The fist two boards have MIRA DDR2 chip and DDR calibration complete successfully with this .bit file The second two boards has ISSI DDR2 chip and DDR calibration fails with the same .bit file. What are the MIG setting differences for these DDR2 chips?