Clyde

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Everything posted by Clyde

  1. Hi, I installed the version for 2017.4, and that install had a failure, but completed. The failure was not due to dependencies. Petalinux would run, but during the project build it had what appeared to be internal software errors. Clyde
  2. The last post was sitting in my browser... and not posted until just now. I have a fresh copy of UG1144 for 2017.4. I read on the internet that in order to tell what version of Petalinux you have installed, to issue this command cat $PETALINUX/.version_log https://unix.stackexchange.com/questions/379242/how-to-know-the-petalinux-version and it says I have 2019.2, which is not what I desire. So, I am going to try a new, fresh install. I have verified the installation requirements are met. Clyde
  3. Hi, Thank you for the pointed questions. I think they are on target and will help me move forward. Sorry for the delay in my answer as I have been busy with other Zynq stuff. First, I cannot find the folder .petalinux/metadata. I looked in "my computer" and turned on hidden folders, but I am clearly not looking in the right place. So I don't know what version for petalinux is in that folder. When I downloaded the distribution, and that was a few months ago, I likely chose the latest version, guess is 2019.2. I have since read that it makes sense to use the version which goes w
  4. A pencil sketch of the schematic would be great for readers to help you. Does not need to be elegant and you can shoot it with a smart phone. Include the power supply please. Clyde
  5. Hi, Thank you for the pointed questions. I think they are on target and will help me move forward. Sorry for the delay in my answer as I have been busy with other Zynq stuff. First, I cannot find the folder .petalinux/metadata. I looked in "my computer" and turned on hidden folders, but I am clearly not looking in the right place. So I don't know what version for petalinux is in that folder. When I downloaded the distribution, and that was a few months ago, I likely chose the latest version, guess is 2019.2. I have since read that it makes sense to use the version which goes w
  6. Here is a link to a good article on sine tone generation which talks about doing it without a table. I have done this myself in a DSP. Should be simple enough in an FPGA. http://www.claysturner.com/dsp/1st_OSC_paper.pdf HTH Clyde
  7. The Zynq is an amazing device. Early on I was going to blink an LED with a loop in C on one of the processors. So, I put a delay loop for (i=0; i< 10000; i++) etc. I had to make the delay counter a billion! I still have a lot to learn. Countless hours of entertainment. CRS
  8. Thank you for the reply. I am WFH and putting together a build that will run on Ultrascale hardware at work, and I thought I would try the simple version at home. Not a big deal. I can still prove the concept. While we are here, is it possible to access the MII interfaces from the PL fabric on the Zynq device, if one disables their use from the ARM processor? I have read the Technical reference manual, but there is a lot of material to digest there. Clyde
  9. What I/O standard should I select if I want to drive a high speed PMOD port differentially? and for Receive? It seems like with Vcco at 3.3V this is not possible with the native I/O buffers. Clyde
  10. Sorry, I will rephrase my question with much more detail and clarity, but for now, one thing that I don't understand is Petalinux seems to be grabbing Yocto files in the build that go with a later version of Vivado. That is, from 2019.2 when I am using 2017.4. Again, I will will spell out exactly what I am doing and where it falls apart. So much is right... it just dies at the very end of the build, so, I am very close and I have a whole lot correct.
  11. Well, then, if you want a crimp terminal that goes into a housing, I would recommend Harwin for this kind of thing. I don't have a part number, but they make the receptacle that is a single, goes on the 0.025 post, with crimp terminals. This is the connector you see on JTAG programmers. My bet is that Harwin makes the compliment, with pins. Clyde
  12. Go with the Sullins part above. If you want a board designed... let me know.
  13. I was wondering if he ever found replacement hardware for his application. I'd be interested in do a similar design if he wanted to entertain that, custom, the way he wants it. I did my own shield for the arty for audio in and out. Clyde
  14. Perhaps a schematic, part number or block diagram would help users help you.
  15. I wish I could at the very top level of the forum section have the option to search for posts by date, specifically most recent. I have received help from the forum and would like to give back... but so many posts are so old, they are not relevant most likely. Maybe this feature exists, but it is not obvious to me. Clyde
  16. I am re-designing an LED display module, similar to the PMOD SSD. It has 8 digits (I like LEDs) which are multiplexed. It requires two PMOD ports. I have used the prototype successfully on both the Arty A7 and the Zybo Z7. The current design blocks JA and JD on the Arty and JB and JE on the Zybo. The plan in the next revision is to have a bypass connection so that those ports are available for other use. It does not interfere with JA on the Zybo. I would provide a blank board, parts list (one part) and my Verilog HDL driver for it. Currently the design operates in a hexadecimal mode,
  17. Did you ever resolve this issue? Clyde
  18. To each his own. I have had to work with parameterized code (not mine) which is almost unusable and unreadable, and for me, readability is king. Properly done, I will agree with you. Clyde
  19. I have worn out my USB connector and will have to put in a cable, short, and overmold it hot melt glue, or go buy another one. My zybo has a power switch which saves the connector. A good quality micro USB connector should have at least 10,000 cycles. Clearly, the one on the Arty is the cheapest one they could find without regard to quality. Clyde
  20. In my experience the efforts to parameterize a design rarely pay off. A byte is going to be 8 bits for a long time. There is readability lost in the parameterization. I will stick with straight code with an emphasis on readability. Just my $0.0256 worth.
  21. Samtec makes one... Do you want a board design to go with it? Clyde
  22. I would be careful in making a substitution of the LM358. Although it is a very old part, it has some desirable performance characteristics that make it superior, especially at voltages near ground in a single supply application. Be careful of the product selector guide at Digikey when it comes to operational amplifiers. The supply voltage numbers in the selector guide do not always line up with the data sheet. HTH If you post the whole circuit with the op-amp, I might try and simulate it for you. A complete schematic please.
  23. All, I am building my linux image for the Zedboard and it all goes along swimmingly until the very end when it dies with the rootfs. The message I get is The postinstall intercept hook 'update_font_cache' failed. This is the only error in the whole process. One other concern I have, is in watching the build happen, I see what looks like files associated with Vivado 19.2 being used. My build was created with 17.4. However, none of these files being grabbed from the Yocto project throw any errors. Any hints here? BTW, I don't want to move up to 19.2 at this time. Clyde
  24. If you are going to PCB, there is 0879110611 from Molex, and PRPC006DBAN-M71RC from Sullins. Be careful as there is an error on the Molex data sheet.... I will admit, I have not actually used the Molex part, but have it designed in. The 3D step model for it shows that it will fit the same as the Sullins part. It's 5.12 mm from the left edge of the black housing to the center of the two rows of pins.
  25. You are losing me in your problem description without a block diagram. I too want to know how to go from the PS to PL and I think the answer lies in UG585. My guess is it involves using the MIO not as a means to access peripherals, but just a general interface. It is curious that when configuring the ZYNQ, one can completely disable all of the peripherals. There are lots of things to learn. Clyde