Clyde

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  1. I think I am largely on my way. I just built a quick little hello world hardware platform, created a bitstream and it's in the FPGA. Now its up to me to remember how to get the SDK to play, but it will come. Thanks again. Clyde
  2. Ok, now I see that by checking the uart boxes in the I/O configuration, the serial port is there.... it just does not show up in the diagram. I think with help with the concat logic and the PMOD repository question I am good to go. What I have learned is Zynq is not so external component intensive as a Microblaze design is. Clyde
  3. Ok, this is helpful, but in your diagram there is no external serial port visible to me. I see in the Zynq setup the Uart is enabled, but how to get it out? What I am really trying to do, to get started is to build a simple linux platform with a serial port, buttons and LEDs and the wifi so I may try my hand at embedded linux. This is a really simple hardware platform and I feel like I am the first person in the world to do this (can't be true). I am attaching a screen shot of the Project management screen and the boards tab. When I right click on any of the PMODs, I do not get any choices to connect up the Wifi module. Lastly, In a previous attempt where I was "magically" able to get the wife module on PMOD JC, I did hook up the concat block and enable the interrupt as you did, but apart from changing the width of the ports on the concat, I have no clue as to the logic function it is to perform. I stumbled across a Vivado library with PMODs, which I added as IP, but I don't remember where I found it, nor do if I know it is correct. In all of this I realize this is a very powerful system and I am so close, yet so far. Thanks for your help thus far. Clyde config.pdf
  4. I should add the block design was created without any manual wiring, just block automation and connection assistance at the appropriate times. Clyde
  5. What I did was download the newest board files and put them in place and built an existing, working microblaze design on my Arty-35. This all worked and I was able to generate a bitstream. Then I created a new design for the Zybo z-10, essentially the same design and if I recall correctly, I got through the implementation phase, but bitstream failed, as it should. The LEDs are all in the wrong place and the clock too, etch. This failure all made sense. Then I created a new block design, simple, and the implementation fails. Attached is the block design. Linux1.pdf
  6. I am still lost. I have installed the latest repository and built a block design with the zynq uart, and a gpio. It won't implement. Place Design[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 1 sites. Term: uart_rtl_rxd [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 3 | LVCMOS33(3) | | | +3.30 | YES | | | 35 | 50 | 5 | LVCMOS33(5) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 8 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | sws_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y2 | P15 | | | | sws_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y41 | W13 | | | | sws_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y32 | T16 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | leds_4bits_tri_o[0] | LVCMOS33 | IOB_X0Y54 | M14 | | | | leds_4bits_tri_o[1] | LVCMOS33 | IOB_X0Y53 | M15 | | | | leds_4bits_tri_o[2] | LVCMOS33 | IOB_X0Y99 | G14 | | | | leds_4bits_tri_o[3] | LVCMOS33 | IOB_X0Y93 | D18 | | | | sws_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y61 | G15 | * | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances I implemented a microblaze with the same boards files, and that implemented, but failed, of course on the bitstream generation. What could I be doing wrong?
  7. Clyde

    Pmod wifi SDK problem

    Where is this WifiScan project? The examples folder? I am lost trying to find these sources. I have the hardware platform built just fine. Clyde
  8. Thanks. This was a big help as I was able to build the hardware platform, although it came with warnings about an IP repository I found "somewhere" on the internet with definitions for the PMOD devices, including the WiFi module. I still have no clue if I correctly set up any of the clocks. I set the PS clock to 33.3333 MHz (which was a difference) because that is what is used on the Z7-10. However, there is an lot of handwaving when it comes to the application software. Where to find that? Where is the proper IP repository for the PMOD devices? To answer your earlier question, I have tried 2017.4, 2018.2 and 2019.2. I have given up on 2019.2 as I have not been able to figure out Vitis at all. At least with the other two, SDK is still there. I tried all three believing it was a version issue, which it is not. Clyde
  9. Are there any plans to update the board files for the Zybo Z-10? Lots of things are missing from it such as the DDR3 component and the pulldowns for the PMODS, such as for the WiFi. The Arty board files seem to be complete, including DDR3. I am trying to get the Internet of things example running and the video is great, but it is not all there. A pdf of the finished block design would be a tremendous help.. I have scoured the internet and nothing comes up to help. Likewise, many examples are posted which claim to be a compiled and working example of some of the demos, but they are all broken in some fashion or another. I have spent $250 on hardware that I can't get to go. Either I am totally missing something so fundamental, or the board files are faulty. I have been able to Microblaze designs to work on the Arty, but I am stuck with the Zybo.
  10. I did a design for my Arty 7-35 board with 8 digits of 7-segments. It is a multiplexed display and the design could be purchased at Osh Park. Let me know if you are interested as I have nice verilog HDL to drive it. Clyde