According to the response by jpeyron:
I haven't done this project, but went through upgrading the Out Of The Box demo from my Zybo Z7 020 board from 2016.4 to 2018.2, which has a playback version of the DMA for audio. I have completed that and have it working and learned a lot. But I installed and worked with the 2016.4 version of the tools so I could build and run the project, then peruse the code. I am about to get into this project myself, so I'm interested in your results.
Did you do what was suggested?
1: The version IS important. if you are using a new version of the tools (2018.2 vs 2016.4) you have to tell the tcl what version you are running, I believe it's because the IP's are versioned. So, I would make the edit as outlined, then load the project, upgrade the ip cores. Then I would do the next steps, create wrapper and generate the bitstream.
2: There is a software component that has to be tied to the hardware component and that has to be done through the SDK. I believe the software component has to be upgraded through a new hw_handoff component (generated by exporting hardware with bitstream), then importing the correct projects in the SDK, and then creating a new board support package which will create a new fsbl project (IIRC).
Then you can program the Zync, once you've set up the SDK project properly.
Lastly, if you don't want to go through all of that, I didn't for the demo project as it was too much for a newb just starting out with the tools, I went to Xilinx and downloaded Vivado 2016.4 and checked the SDK, so I didn't have to do a separate dl for that too. You can have multiple versions of the tools on the machine at once. This way you won't have to go through the extra layer of determining what is different between the two versions and determine the cause and subsequent resolution just to get to a working project.
Thanks for the input Jon. In addition to starting the ticket with Xilinx I started a search on eclipse not responding and got lots of hits. I'm sorting through that now. And a awaiting a reply from Xilinx support. I will apprise as to the outcome. From the eclipse threads it might be as simple as having the correct version of java installed.
Thank you for verifying the project creation script. Yes, I had done what you did. I also ran it without the "./" prepended and got the same results. However, what I did notice was your path to the .tcl file and mine were different in that none of your directories had a space in the name. I had my projects in a folder named Xilinx Projects. I could cd to it using the old DOS trick of putting quotes around the path. Apparently tcl has problems internally when operating on folders with a space in the name. I admitted I am a newb. I made a new directory without a space, extracted the zip to that folder, opened Vivado 2016.4, cd'ed to the project directory and ran the script with the ./ . Now I have a working project to explore. I can't thank you enough.
Yes, I have the ZYBO Z7-20.
I will look into those threads.