ArKay99

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Everything posted by ArKay99

  1. Not trying to get in the way of jpeyron's help, as I"m a rank newb here and not trying to step on any toes, I've seen this error before, and I would wait until this can be confirmed as the source and/or a possible solution put forward. Are you running this on Ubuntu? It seems make is trying to find a 32 bit tool and/or libs that haven't been installed according to what I've seen. This is from an old thread... https://www.microlab.ti.bfh.ch/wiki/huce:microlab:tools:linux-client:xilinx-vivado arm-xilinx-eabi-gcc The SDK is shipped with a 32bit compiler so you may ne
  2. I looked at the project referenced, but couldn't get into it at this time. However, there were a few things that were misleading, at least to me. Specifically, it appears that in step 11, the author has the reader generate a new BSP for standalone, however, all the subsequent references are for FreeRTOS. The illustrations show standalone and no FreeRTOS is shown. This would have lead me to try and make the BSP using standalone parameters even though it was named RTOSDemo_bsp. It also seems that is what happened to you as the SDK is complaining about something not being available for make to in
  3. Thanks for the update. Since I've been working with the rgb2dvi component I was intrigued. I vote for door number 3.
  4. Hi BogdanVanca, Thanks for the info as I assumed that what those values were for. I was looking for a 'sanity check' because warnings are warnings and I at least like to understand why. Also, the DDR on my board being intermittent and not knowing why was becoming frustrating to say the least. Here is what I did to arrive at my new set of values which seem to have fixed my issue. All this assumes that the preset.xml file is from a Zybo Z7 Rev B board. I have no way of determining the trace lengths without gerbers, and even then I don't have the tools to get a measurement that precise. I wo
  5. Good news. I am curious as to how you resolved the issue.
  6. A follow up on this. I queried on this at Xilinx forums and got many hits relating to this as far back as 2016.1. After reading quite a few threads and responses, it appears that the negative values seem to be a default value that gets installed in the presets.xml file. A few remedies suggested were to leave them alone they will be ok, even though they may trigger warnings, to editing the values in the presets.xml to positive values. A Xilinx employee suggested to edit the file to have 0.001 in all the fields and make sure Write leveling, Read gate, and Read data eye are checked. There are oth
  7. I've been working with my Zybo-Z7-20 board for about 6 weeks now and have been having a hard time with anything having to do with the DDR. If I built and run the OOB demo using Vivado 2016.4 It ran, sort of. I would sometimes get could not write to memory 0x0010000 errors when trying to load a new change into the memory. When I tried to run the demo in Vivado 2018.2, it would give the same message, but none of my breakpoints would get hit and the program in flash would only run. If I set the linker file to run from OCM it would run, but not that well. I built the Hello World example and it ran
  8. I looked at your constraints file and one thing puzzles me. You've constrained the clock to be a higher frequency than the 'standard' clock frequency in the file. In the dvi2rgb documentation there is this info on the TMDS clock constraint: The TMDS clock input Clk_p/n is constrained in the IP to the maximum DVI clock frequency, 165 MHz. On some architectures this might result in timing impossible to meet. Depending on the application, if a lower pixel clock frequency is acceptable, the clock can be constrained on top-level, which will override the IP-internal constraints. For example,
  9. Thanks so much. That was painless. 😉
  10. Thanks for the info. CPU from the overview is: Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz 4.00 GHz 16 gig 1866 ram System type: 64-bit Operating System, x64-based processor. OS is Windows 10 Pro 64 bit. I'm thinking that even though I'm running a 64 bit processor and 64 bit Windows I should dl the 32-bit PC (i386) desktop image, specifically the: ubuntu-16.04.3-desktop-i386.iso? Thanks for the start procedure for the vm, no need to outline the steps.
  11. I'm a newb with Linux or Ubuntu, but want to install the version I need to get Linux working on my Zybo Z7 with the project. Been to the Ubuntu forum, signed up and asked the question and got several answers that didn't seem quite right about the version of both the OS, the LTS vs GA and the kernel, where they exist, etc. I've got a clean Win 10 machine and going to put VMWare on it and run Ubuntu on it, but it's clear as mud how I go about getting and installing 16.04.3. OR do I need that as the minimum and can install the most current version.. 18.xx something? What have the develo
  12. As I said, I haven't done this project yet and it's possible that the SDK isn't used as the Zynq can be programmed and run with just the PL. However, when I looked at the project description I saw this... This says to me that the hardware has already been built in Vivado and the next step is to work with the SDK, by either importing the hardware handoff or generate the bitstream in Vivado, export the hardware, and include the bitstream in the export, which will create the hardware handoff, then launch the SDK from the menu in Vivado. So, if you've already done the Vivado update pa
  13. According to the response by jpeyron: I haven't done this project, but went through upgrading the Out Of The Box demo from my Zybo Z7 020 board from 2016.4 to 2018.2, which has a playback version of the DMA for audio. I have completed that and have it working and learned a lot. But I installed and worked with the 2016.4 version of the tools so I could build and run the project, then peruse the code. I am about to get into this project myself, so I'm interested in your results. Did you do what was suggested? 1: The version IS important. if you are using a new version of the t
  14. Well, I applied for the ticket and was 'approved' at the Xilinx Service Portal, but upon entering it, I have no way to enter a ticket and am left with the only choices of the Forums, the FAQ's, or the Knowledge Base, of which I spent almost 2 days perusing and searching and have come up empty. I suppose because I don't have a corporate email account, and a third party product, they're not interested. At this point, I'm not sure what to do. I'm also glad that I didn't pay the $595 for a node locked SDoC license! I have also exhausted the threads relating to Eclipse and their memory problem
  15. Thanks for the input Jon. In addition to starting the ticket with Xilinx I started a search on eclipse not responding and got lots of hits. I'm sorting through that now. And a awaiting a reply from Xilinx support. I will apprise as to the outcome. From the eclipse threads it might be as simple as having the correct version of java installed.
  16. I think you mean the .pfm file referenced in the custom platform generation tutorial video? The ones from Xilinx are at Xilinx\SDx\2018.2\platforms. However, I too would like to know where the Digilent ones are that are referred to in the video at 1:11 here https://www.xilinx.com/video/soc/sdsoc-custom-platform-generation.html I also, have not been able to find them...they may not exist which would mean they have to be created from scratch as a custom platform.
  17. First of all, I'm not sure if this is the right forum for this, as this is a question about tool installation and usage. If it is in the wrong place perhaps a mod can move this or provide a suggestion as to the right place to ask this. I had SDoC 2018.1 installed along with Vivado and Vivado HLS and subsequently installed 2016.4 Vivado, SDK, and Vivado HLS to work with the OOB project for my Digilent board. I got that working and was able to go through much of the project all the way to debug and program and verify with the SDK and the contained C code. A few days later I wanted to start
  18. Thank you for verifying the project creation script. Yes, I had done what you did. I also ran it without the "./" prepended and got the same results. However, what I did notice was your path to the .tcl file and mine were different in that none of your directories had a space in the name. I had my projects in a folder named Xilinx Projects. I could cd to it using the old DOS trick of putting quotes around the path. Apparently tcl has problems internally when operating on folders with a space in the name. I admitted I am a newb. I made a new directory without a space, extracted the zip to that
  19. Thank you JColvin. I wasn't expecting a response on father's day, so double thanks. An FYI, I hooked up an HDMI monitor and there is a test pattern being tx. I haven't checked the rx. I'll wait for your response tomorrow. In the meantime I'm going to see how to download the bitstream from the Zybo to a file on my computer, just so I at least have that.
  20. I just purchased a ZYNQ-7020 Development board for my development and learning purposes. Just out of the box, it's pretty amazing and I'm anxious to dive in and start kicking the tires...so here's my question and resulting dilemma. I found what appears to be the code at the bottom of the product page. I downloaded and installed it and upon reading the readme discovered that it will only work with Vivado 2016.4. So, I downloaded and installed 2016.4 from the archives, after I discovered that Vivado can have multiple versions coexist on the same machine (thank you Xilinx). After the install
  21. I answered my own question. I went to the link and downloaded the installer for SDx and installed that, which gave me Vivado, Vivado HLS, and DocNav, all in the 2018.1 format. Then it was a simple matter to license the installation and I was up and running in a few minutes...after a lengthy download. My next challenge was to find the code for the OOB demo that the ZYNQ -7020 ships with. I found that at the bottom of the ZYBO Z7 product page. I downloaded that and opened the readme to find out it would only work with 2016.4. i created a new thread to address that.
  22. Hello all. I have been programming in C/C++ for almost 30 years and before that in assembler and BASIC on an Apple 2...yes, a long time ago! I've also had several years experience doing embedded design with Atmel products and PCB design. I have been learning Verilog and VHDL for the last couple of years and about 6 months ago bought a Lattice MachXo2 Breakout board and a few different Codec boards aimed at audio encoding/decoding. I've also done a bunch of work with the Mico8 and it's environment and integration. My short term goal is to learn about digital filtering as applied to accelerate