Sridhar Prasath Aruppukottai Ganesan

Question: writing data(from UART0) to DDR memory and reading the processed data(to UART1) from DDR

By Sridhar Prasath Aruppukottai Ganesan, June 20, 2018 in FPGA

• Awaiting best answer

• zedboard
• uart0 and 1

Question: uartlite interrupt

By Sridhar Prasath Aruppukottai Ganesan, August 14, 2018 in FPGA

• Awaiting best answer

• uartlite
• interruptsystem

Question: doubts on uartlite interrupt

By Sridhar Prasath Aruppukottai Ganesan, August 2, 2018 in FPGA

• Awaiting best answer

Question: gsm module connection with zedboard

By Sridhar Prasath Aruppukottai Ganesan, July 14, 2018 in FPGA

• Awaiting best answer

• gsm module hilo
• zedboard

Question: stdin and stdout for uartlite

By Sridhar Prasath Aruppukottai Ganesan, July 27, 2018 in FPGA

• Awaiting best answer

• zynq
• xilinx sdk

Question: PmodGps connection to Zedboard

By Sridhar Prasath Aruppukottai Ganesan, July 11, 2018 in FPGA

• Awaiting best answer

• pmodgps
• zedboard

Question: Zedboard- connected GPS device on UART0- Viewing streaming gps data on PC terminal

By Sridhar Prasath Aruppukottai Ganesan, June 22, 2018 in FPGA

• Has best answer

• zedboard
• uart0

Question: Accessinng OCM memory from PL side

By Sridhar Prasath Aruppukottai Ganesan, June 28, 2018 in FPGA

• Awaiting best answer

Question: connecting IP blocks for PL side - project includes GPS module, GSM module,Memory, Debug TAP controller

By Sridhar Prasath Aruppukottai Ganesan, June 13, 2018 in FPGA

• Awaiting best answer