HI,Jon,
Yes, Yes - Indeed we don't know what under the hood of Vivado / Vitis and that brings all sorts of problems. I liked best when we had to develop all the VHDL files and nest to one another. That was complex but we had all under control.
They try to automatize everything for the user but when a problem arises, it is never easy to solve, nor there is enough information to guide us in the process of solving it.
I did some more tests and found out that those Makefile errors only appear when I use a certain custom IP that I created. Vivado compiles it without any warning and xsa file is generated without a problem. But in Vitis, the presence of that IP in the project causes the makefile error to pop up.
Would you have any hint to get me going ?
Thanks
Antonio