Antonio Fasano

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Antonio Fasano last won the day on September 10 2018

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About Antonio Fasano

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  1. Antonio Fasano

    Discount for purchase of large quantity of ARTY-Z7

    Hi, Jon, I did not see any way to get in touch with sales through the website. Would you happen to know the contact info for any sales person that I can reach out to ? Thanks Antonio
  2. Hi, Guys, Is it possible for me to have a price break if I purchase, say, 200 ea or 300ea of the ARTY-Z7-20 board ? Thanks Antonio
  3. Hi, Guys, I am trying to write and read from the micr SD card on Arty-Z7-20. I took a look of one of the examples and one of the required libraries is "ff.h" I suppose it has the prototypes for the functions needed to operate the SD card on the Arty. My SDK cannot find that library. What should I do ? Thanks Antonio
  4. Hi, Guys, I am working iwth Vivado 2018.1 Suppose I have a complete project with bitstream, Hardware files and SDK files in directory c:\Arty_Test If from within Vivado I save the project to another directory, say c:\Arty_Test2 (Even with option "Import All files to new project" clicked) , the new project software files will not open correctly when I invoke SDK. It still looks for files in the original directory. Is there a way to make sure it will save all files and update all references to the new directory ? Thanks Antonio
  5. Antonio Fasano

    GPIO IP outputs

    HI, Jon Thank you very much. Now I know what went wrong. In the constraints file I was writing gpio(0), gpio(1), etc. By looking at your example, I noticed that the correct spelling is gpio[0], gpio[1], etc. I changed it in my project and it ran fine. Once again thank you very much for your time and for your guidance. I owe you another one !!! Regards, Antonio
  6. Antonio Fasano

    GPIO IP outputs

    Hi, Jon I tried to make external the while GPIO output and not only the _t signals. The new wrapper file becomes much similar to the one that works, but the placement error continues to appear. This is the link to the project archive that is working: This is the link to the modified project that is not working The zynq chip is XC72020 CLG400ABX1701 D5348119A Thank you for your support. Antonio
  7. Antonio Fasano

    GPIO IP outputs

    Hi, Jon, I inspected both the older wrapper file and the neweer (After I made the customs 13 outputs external instead of the shield pins.. The older file shows a lot of references to the shield pins, including i / o and t sufixes (See below) shield_dp0_dp13_tri_i(13) => shield_dp0_dp13_tri_i_13(13), shield_dp0_dp13_tri_i(12) => shield_dp0_dp13_tri_i_12(12), shield_dp0_dp13_tri_i(11) => shield_dp0_dp13_tri_i_11(11), shield_dp0_dp13_tri_i(10) => shield_dp0_dp13_tri_i_10(10), shield_dp0_dp13_tri_i(9) => shield_dp0_dp13_tri_i_9(9), shield_dp0_dp13_tri_i(8) => shield_dp0_dp13_tri_i_8(8), shield_dp0_dp13_tri_i(7) => shield_dp0_dp13_tri_i_7(7), shield_dp0_dp13_tri_i(6) => shield_dp0_dp13_tri_i_6(6), shield_dp0_dp13_tri_i(5) => shield_dp0_dp13_tri_i_5(5), shield_dp0_dp13_tri_i(4) => shield_dp0_dp13_tri_i_4(4), shield_dp0_dp13_tri_i(3) => shield_dp0_dp13_tri_i_3(3), shield_dp0_dp13_tri_i(2) => shield_dp0_dp13_tri_i_2(2), shield_dp0_dp13_tri_i(1) => shield_dp0_dp13_tri_i_1(1), shield_dp0_dp13_tri_i(0) => shield_dp0_dp13_tri_i_0(0), shield_dp0_dp13_tri_o(13) => shield_dp0_dp13_tri_o_13(13), shield_dp0_dp13_tri_o(12) => shield_dp0_dp13_tri_o_12(12), shield_dp0_dp13_tri_o(11) => shield_dp0_dp13_tri_o_11(11), shield_dp0_dp13_tri_o(10) => shield_dp0_dp13_tri_o_10(10), shield_dp0_dp13_tri_o(9) => shield_dp0_dp13_tri_o_9(9), shield_dp0_dp13_tri_o(8) => shield_dp0_dp13_tri_o_8(8), shield_dp0_dp13_tri_o(7) => shield_dp0_dp13_tri_o_7(7), shield_dp0_dp13_tri_o(6) => shield_dp0_dp13_tri_o_6(6), shield_dp0_dp13_tri_o(5) => shield_dp0_dp13_tri_o_5(5), shield_dp0_dp13_tri_o(4) => shield_dp0_dp13_tri_o_4(4), shield_dp0_dp13_tri_o(3) => shield_dp0_dp13_tri_o_3(3), shield_dp0_dp13_tri_o(2) => shield_dp0_dp13_tri_o_2(2), shield_dp0_dp13_tri_o(1) => shield_dp0_dp13_tri_o_1(1), shield_dp0_dp13_tri_o(0) => shield_dp0_dp13_tri_o_0(0), shield_dp0_dp13_tri_t(13) => shield_dp0_dp13_tri_t_13(13), shield_dp0_dp13_tri_t(12) => shield_dp0_dp13_tri_t_12(12), shield_dp0_dp13_tri_t(11) => shield_dp0_dp13_tri_t_11(11), shield_dp0_dp13_tri_t(10) => shield_dp0_dp13_tri_t_10(10), shield_dp0_dp13_tri_t(9) => shield_dp0_dp13_tri_t_9(9), shield_dp0_dp13_tri_t(8) => shield_dp0_dp13_tri_t_8(8), shield_dp0_dp13_tri_t(7) => shield_dp0_dp13_tri_t_7(7), shield_dp0_dp13_tri_t(6) => shield_dp0_dp13_tri_t_6(6), shield_dp0_dp13_tri_t(5) => shield_dp0_dp13_tri_t_5(5), shield_dp0_dp13_tri_t(4) => shield_dp0_dp13_tri_t_4(4), shield_dp0_dp13_tri_t(3) => shield_dp0_dp13_tri_t_3(3), shield_dp0_dp13_tri_t(2) => shield_dp0_dp13_tri_t_2(2), shield_dp0_dp13_tri_t(1) => shield_dp0_dp13_tri_t_1(1), shield_dp0_dp13_tri_t(0) => shield_dp0_dp13_tri_t_0(0), while the new wrapper file only shows some _t ocurrences of the gpio_io_t_0 signals That´s all that appears in the new wrapper. gpio_io_t_0(12 downto 0) => gpio_io_t_0(12 downto 0), There are several IOBUF components that do not appear in the new wrapper also. Perhaps instead of re-generating the wrapper I should keep the older wrapper and only change the signals, right ? But what about the other _o _i signals ? Thanks Antonio
  8. Antonio Fasano

    GPIO IP outputs

    Hi, Jon, That was exactly the first thing I did. I followed your instructions thoroughly with the gpio_io_t entries. Then I changed it to gpio_io_o to see if the results would be any different. But the errors were the same. Anything else I could try ? Thanks Antonio
  9. Antonio Fasano

    GPIO IP outputs

    My Vivado version is 2018.1
  10. Antonio Fasano

    GPIO IP outputs

    Attached. Thanks CONSTRAINT.xdc X4000_wrapper.vhd
  11. Antonio Fasano

    GPIO IP outputs

    Hi, Jon I did exactly what you say in your post but I keep getting placement errors: Portion of the wrapper file: SDATSAI2 => SDATSAI2, gpio_io_o_0(12 downto 0) => gpio_io_o_0(12 downto 0), shield_dp26_dp41_tri_i(15) => shield_dp26_dp41_tri_i_15(15), Portion of hte XDC file: set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(0) }]; set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(1) }]; set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(2) }]; set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(3) }]; set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(4) }]; set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(5) }]; set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(6) }]; set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(7) }]; set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(8) }]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(9) }]; set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(10) }]; set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(11) }]; set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o_0(12) }]; Errors I get [Place 30-58] IO placement is infeasible. Number of unplaced terminals (13) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 13 sites. Term: gpio_io_o_0[0] Term: gpio_io_o_0[1] Term: gpio_io_o_0[2] Term: gpio_io_o_0[3] Term: gpio_io_o_0[4] Term: gpio_io_o_0[5] Term: gpio_io_o_0[6] Term: gpio_io_o_0[7] Term: gpio_io_o_0[8] Term: gpio_io_o_0[9] Term: gpio_io_o_0[10] Term: gpio_io_o_0[11] Term: and gpio_io_o_0[12] What am I doing wrong ? Thanks Antonio
  12. Antonio Fasano

    GPIO IP outputs

    Hi, Guys, I am using the AXI GPIO (2.0) IP in a ARTY-Z7-20 projetct. The output of the GPIO goes to teh shield dp0 dp13 outputs. I would like to attach outputs from dp0 to dp12 only to that IP. I would like to leave dp13 to another IP in the project. How can I do it ? How can I split DP0-DP12 and link them to the AXI GPIO IP ? Thanks Antonio
  13. Antonio Fasano

    MicroSD Card on the ARTY-Z7-20

    Thanks Jon, I will try !! Antonio
  14. Antonio Fasano

    MicroSD Card on the ARTY-Z7-20

    Hi, Jon Thank you for your answer. I already did the boot.bin file and it is working fine. Is there any tutotial that has an example on how to write/read data to the microSD card ? Do I need to add an IP to the design ? Thanks Antonio
  15. Antonio Fasano

    MicroSD Card on the ARTY-Z7-20

    Hi, Guys I am configuring my ARTY-Z7-20 through the microSD card. I would like to add data to it in binary form and would like to retrieve that data in a later session. How should I do it ? Do I need to add the SD Card as an SD CARD IP in my project ? Are there any examples about that ? Thanks Antonio