Antonio Fasano

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Antonio Fasano last won the day on September 10 2018

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About Antonio Fasano

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  1. Hi, Guys, I am trying to add Sound In and Out to the ARTY-Z7-20. I would like to read in mic data and output it to Speaker data. I have the PMOD I2S2 but I cannot find any IP for it. How do you suggest I proceed with this ? Thanks Antonio
  2. Hi, Guys, I am looking for a way to grab high resolution images with the Arty-Z7-20. I need to add this functionality to my existing design. Is there any Camera PMOD that can be used with the Arty-Z7-20 and already has an IP for it ? Is there any single IP (Paid or not) that I can use to get images from the HDMI In connector ? Any suggestions you can give me are welcome. I looked through the HDMI-IN demo, but adding all those blocks to my existing design will be cumbersome. I am looking for a singne IP for simplicity ... Thanks Antonio
  3. Hi Cristian, Thank you. But I am afraid the link you gave me points to this very same page ... Are you sure it is correct ? Thanks Antonio
  4. Hi, Guys, Where can I find an example project for the ARTY-Z7-20 that uses the HDMI imaging ? Thanks Antonio
  5. HI, Zygot, OK. I got you. Good advice. I will do that. Thank you !!! Antonio
  6. Hi, Guys, Suppose I am using a certain IP that is located at directory named AA c:\VivadoProjects\AA\ I have exported the project to another directory (BB) and I have given the project another name c:\VivadoProjects\BB But the fact is that the new project is still grabbing files from the first directory AA (Specifically one of the IIPs) and If I delete the first directory, the IP gets unresolved. How can I make sure that all the necessary files and IPs are exported to the new directory and no longer need the original directory files ? Thanks Antonio
  7. Hi, Guys, I would like to get image data from a HDMI camera and send it through Ethernet using the Arty-Z7-20. Is there any thread where it is discussed ? Thanks Antonio
  8. Hi, JColvin Thank you very much for your answer. Actually what I need to do is to use some kind of software(Ethernet) driven interrupt. I cannot have a digital input interrupt to the ZYNQ processor. It all needs to be done over the ethernet connection to the computer. Any idea ? Thanks Antonio
  9. HI, Guys, I have a C# application sending/receiving TCP telegrams to/from the ARTY-Z7-20. I am using the lwIP TCP server model, with some modifications to receive commands from the computer and execute some tasks. When I send a TCP stream of, say, A0h, Arty will start executing a task that will take 5 minutes to complete. My VB code keeps waiting for the TCP answer. My question is: Suppose I need to interrupt the task before the 5 minutes runs out. How do you suggest I should do it ? Thanks Antonio
  10. Hi, Guys, I have a project in Vivado 2018.3 on Arty-Z7-20. I have been archiving the project at several points along the development. I noticed that if we take one archived file and decompress it, we need to copy it to exactly the same folder name as the original project . When we don't do it, the SDK project won't open correctly and does not find the developed C project for the project. I wonder if there is a way to get rid of that problem and be able to open that archived project in a folder with another name with correct SDK results. Thanks Antonio
  11. Hi, Guys, Sorry for this question. I am developing a project on Arty-Z7-20 on Vivado 2018.3 AFter I generate Bistrstream and export hardware and Launch SDK, when I get to the point when I need to download my project to the ARTY board, I get two choices of Hardware platforms to choose from: MyProject_wrapper_hw_platform_1 or MyProject_wrapper_hw_platform_2 My question is: Where do those 02 different designs coma from ? I noiced that the first one is an old implementation, when the project was not as developed as it is now. I did not define 02 variants of VHDL implementation in Vivado. Why do 02 options appear in SDK ? Thanks Antonio
  12. Hi, Jon, I went back to the old computer and VIVADO 2018.1. I did the same change to the IP. Updated the IP and tested the new solution. It worked flawlessly. Then I copied the whole project to the new computer with VIVADO 2018.3 and upgraded the project to 2018.3. Recompiled everything and the new bitstream works OK. My concern now is if I make any change to the IP in 2018.3, will it get to the resulting bitstream ? What hints should I look for to know that it has eventually not been processed correctly. Those kinds of problems take days to figure out the solution ... Is there a short manual where we can find an explanation for the file structure of a VIVADO project ? Those endless XILINX manuals take months to read and information is not objective in almost all of them ... Thanks Antonio
  13. Hi, Guys I am facing another difficulty with Arty-Z7-20. One of the custom IP´s that I made has only one output (square wave). I change the output to Output <= ´0´ in the vhdl file using the"Edit IP in Packager" option Then I re-generate bitstream in the main project after updating the IP. The resulting bitstream seems to be picking the IP vhdl from somewhere else, because in the resulting design, the square wave signal is still present. (The IP packager shows the correct path to the file, though...) It seems that the vhdl for the IPs come from somewhere else. No matter what I change in them, the result remains the same ... Go figure ... Have you ever seen that behaviour ? Antonio
  14. Hi, Jon, I did just that and it worked !!! Thanks Antonio