bklopp

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  1. bklopp

    Cannot connect PYNQ-Z1 to USB Serial Terminal

    I would try 9600 Baud and use teraterm instead. https://download.cnet.com/Tera-Term/3000-2094_4-75766675.html
  2. I finally got it working by following instructions from a forum post on xilinx forums: https://forums.xilinx.com/xlnx/board/message?board.id=EMBEDDED&message.id=43256#M43256 I'll look at your projects and figure out where I'm going wrong, since the fix recommended by the dude from xilinx only uses single spi mode (X1), so I imagine it loads quite a bit slower than it could. Because of that, I hesitate to mark this post as the solution. 1) Yes 2) Yes 3) Here are my cache settings. I'm a bit curious why the cache matters. Does the "hello world" application get loaded into it at some point of the programming process?
  3. I regenerated the bit stream with the QSPI flash IP connected to 50MHz and set to Quad. Same result, nothing has been printed to the terminal. I notice that when I press the program button on the nexys video board, the done light (LD15) comes on after about 10 seconds . EDIT: Actually I do get the "SREC SPI Bootloader" output to the terminal, so that C code must be programmed to the spi because it is executing. I'm guessing the bootloader is supposed to boot the helloworld, but that just isn't happening for whatever reason. EDIT 2: I dug into the srec bootloader template code and added prints to see where the code fails. I found out that the spansion chip on the nexys video is not supported, at least by the code that was reccomended by the tutorial. The code halts at line 1920 (line numbers may be different since I added print statments) in xilsf.c.
  4. I have been programming the Nexys video through the USB J12 port, I do have a JTAG HS2 on hand that I can use to program the board with. Do I need to use the JTAG HS2 for this to work? 1) Here is the block design, I am using the 100Mhz clock... that might be a problem: 2) I am able to run the hello world program by run as->launch on Hardware(system debugger) 3) I'm assuming your asking about the linker script: I'm rebuilding the project with the 50Mhz clock to try that out. Thanks.
  5. I have been following this tutorial and have had no luck. I am uncertain about how to configure the QSPI IP, because the tutorial starts assuming that I have done that part successfully, so I am not even sure if this is the root of my problem. I have tried these two configurations of this IP, compiled them, and exported them to the SDK, and none of them solved the problem: I made sure JP4 is in the QSPI position. On step 3.1 in the tutorial, I can see that the FPGA is programmed successfully and I see the following output (since I chose not comment out the VERBOSE define as suggested in the tutorial): While programming the flash on step 4 I notice that my FPGA code is erased from the board (leds I had assigned to outputs turn off). Is that supposed to happen? At the end of the tutorial I get no "hello world" output on the terminal after resetting the board, though the FPGA does seem to program from the flash successfully, so that portion works, but I can't get the C-code to run from the flash. Here is the sdk_console_output.txt so you can see the steps I took in the sdk to program the board.
  6. Awesome, thanks guys that worked for me. I also had to make sure the component definition name matched the "of_component=" name in the interface definition. For anyone with the same problem, here is the working interface definition in the board.xml file: <interface mode="slave" name="sysclk" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sysclk"> <parameters> <parameter name="frequency" value="300000000"/> </parameters> <preferred_ips> <preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/> </preferred_ips> <port_maps> <port_map logical_port="CLK_P" physical_port="sysclk_p" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="sysclk_p"/> </pin_maps> </port_map> <port_map logical_port="CLK_N" physical_port="sysclk_n" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="sysclk_n"/> </pin_maps> </port_map> </port_maps> </interface> And the working component definition in the board.xml file: <component name="sysclk" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clock"> <description>100 MHz Differential System Clock</description> </component> And finally the pins in the pins file <pins> <pin index="00" name ="sysclk_p" iostandard="LVCMOS25" loc="AG29" /> <pin index="01" name ="sysclk_n" iostandard="LVCMOS25" loc="AG30" /> ...
  7. Since you folks an Digilent make these wonderful board files that make it super easy to connect components, I figured I'd make my own for a custom board. The problem is that my design uses a differential sysclock, whereas most Digilent designs use a single-ended sysclock. I have been pouring over the board file chapter in UG895 to figure out how to do this, but unfortunately I haven't found any examples or hints in doing so. A single-ended clock interface in the board.xml file looks like this: <interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description> <port_maps> <port_map logical_port="clk" physical_port="clk" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> Which allows one to click and drag "System Clock" from the board tab into the block design and gives you a clocking wizard with a single-ended clock. I want to be able to do the exact same thing, except instead of spawning a clocking wizard with a single-ended clock, it spawns a clocking wizard with a differential clock, like this: Here is my failed attempt at creating this interface: I used "xilinx.com:signal:diff_clock_rtl:1.0" instead of "xilinx.com:signal:clock_rtl:1.0" and added another port map for the p/n signals. <interface mode="slave" name="sys_clock" type="xilinx.com:signal:diff_clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_diff_clock_preset"> <description>3.3V Double-Ended 100MHz oscillator used as system clock on the board that don't work none good</description> <port_maps> <port_map logical_port="CLK_P" physical_port="clk_p" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_p"/> </pin_maps> </port_map> <port_map logical_port="CLK_N" physical_port="clk_n" dir="in"> <pin_maps> <pin_map port_index="0" component_pin="clk_n"/> </pin_maps> </port_map> </port_maps> <parameters> <parameter name="frequency" value="100000000" /> </parameters> </interface> and I added the following pins to my pin file: <?xml version="1.0" encoding="UTF-8" standalone="no"?> <part_info part_name="xc7a200tffg1156-2"> <pins> <pin index="00" name ="clk_p" iostandard="LVCMOS25" loc="AG29" /> <pin index="01" name ="clk_n" iostandard="LVCMOS25" loc="AG30" /> Which gives me this message: "'System Clock' board component cannot be connected because no possible options to connect." when I try to click and drag system clock into the design: Do I need to edit the preset file, or is the syntax for my interface definition incorrect, or am I missing something else entirely? Any help is greatly appreciated. Thanks in advance
  8. bklopp

    Board file (XML) and Constraints file (XDC) in Vivado

    I assumed the constraints were generated from the pin file, which is referenced by the board file.
  9. bklopp

    Nexys Video DMA Audio Demo is broken

    I followed your suggestion and just downloaded Vivado 2016.4. I tested it and it works on that version.
  10. bklopp

    Nexys Video DMA Audio Demo is broken

    It looks like the interrupt is never being triggered by the DMA. I put a breakpoint inside of the interrupt handler and it never hits it.
  11. bklopp

    Nexys Video DMA Audio Demo is broken

    I created a new empty application project, imported the folders and files from the DMAaudio folder into my project. I could use some clarification on what you mean by "manually importing all the settings from the old one" What settings are you referring to? The settings under the Board Support Package settings? If so, which ones need changed to what? system.mss system.mss
  12. I used the logic analyzer in the Analog Discovery personally, So I would naturally go with the Digital Discovery if I needed more I/O lines since it's a more familiar device and interface for me personally. It looks like the DV509 can operate at faster speeds, but only offers 9 channels instead of the 32 that the Digital Discovery offers. I guess it boils down to what you need more, speed, or more I/O? I don't have any experience debugging I2C or SPI drivers though, so I'm not so sure about that front.
  13. bklopp

    zybo zynq

    What are you trying to do? Edit: I found this link after a quick google search: http://zedboard.org/content/configuring-zynq-spi-interface Hope that helps.
  14. bklopp

    Nexys Video DMA Audio Demo is broken

    Upon importing the SDK project, I get these errors: SDK Log: 09:33:32 INFO : Registering command handlers for SDK TCF services 09:33:33 INFO : Launching XSCT server: xsct.bat -interactive C:\Users\Brandon\Downloads\Nexys-Video-DMA-master\Nexys-Video-DMA-master\proj\DMA.sdk\temp_xsdb_launch_script.tcl 09:33:35 INFO : XSCT server has started successfully. 09:33:36 INFO : Processing command line option -hwspec C:/Users/Brandon/Downloads/Nexys-Video-DMA-master/Nexys-Video-DMA-master/proj/DMA.sdk/design_1_wrapper.hdf. 09:33:36 INFO : Successfully done setting XSCT server connection channel 09:33:36 INFO : Successfully done setting SDK workspace 09:34:10 ERROR : (XSDB Server)ERROR: [Hsi 55-1594] Core intc of version 3.5 not found in repositories 09:34:10 ERROR : (XSDB Server)ERROR: [Hsi 55-1452] Error: running open_sw_design. 09:34:10 ERROR : [Common 17-39] 'hsi::open_sw_design' failed due to earlier errors. 09:34:10 ERROR : (XSDB Server)ERROR: [Hsi 55-1594] Core intc of version 3.5 not found in repositories 09:34:10 ERROR : (XSDB Server)ERROR: [Hsi 55-1452] Error: running open_sw_design. 09:34:10 INFO : Unable to read in MSS file C:\Users\Brandon\Downloads\Nexys-Video-DMA-master\Nexys-Video-DMA-master\sdk\DMAaudio_bsp\system.mss : null 09:34:10 ERROR : (XSDB Server)ERROR: [Hsi 55-1594] Core intc of version 3.5 not 09:34:10 ERROR : (XSDB Server) found in repositories ERROR: [Hsi 55-1452] E 09:34:10 ERROR : (XSDB Server)rror: running open_sw_design. 09:34:10 ERROR : Failed in generating sources 09:34:10 INFO : BSP Project P/DMAaudio_bsp has been successfully migrated. Problems window: fatal error: xparameters.h: No such file or directory userio.c /DMAaudio/src/userio line 54 C/C++ Problem make: *** [src/userio/userio.o] Error 1 DMAaudio C/C++ Problem
  15. bklopp

    how to send large data bytes to pc using TCP-LWIP stack

    So by the sounds of it, you are able to send some data (a byte?) to your PC via Ethernet, correct? And you want to be able to send more data (bytes)? I'll have to see what code you are using on the ARTY side in order to help. Here is some info on sending data in the mean time: http://lwip.wikia.com/wiki/Raw/TCP#Sending_TCP_data