I'm trying to implement IOSERDES block as shown in the attachment on Vivado and couldn't find any idea on how to implement it by using IP blocks.
The idea of my design is to enter 12 bits (000000111111) parallel input to (OSERDES) in DDR mode and then, 2 outputs (serialized data and clock) will be connected to (ISERDES) in DDR mode in order to generate again the same parallel input. A (check module) will be added to check if the received value after applying some delay is the same (000000111111) or not, and according to that, it will generate a signal to the BitSlip in the ISERDES to correct the output.
I have read several documents but it was not obvious how to start implementing that. Also, I'm struggling with finding some tutorials to explain this step by step.
So, could you please help me in detail if possible on how to implement this design? and how to convert the final blocks to Verilog code?
I appreciate any help and sorry for the long post.
Thank you in advance.