Mazen

Hi all, I have an Arty board and I want to use LVDS connections for my project that run at 80 MHz. From here, JB and JC are the high speed pmods that should be used for LVDS and connect this to an ADC chip. Actually, this is my first time using this connection. So, My questions are: 1- What is the digilent's Pmod that I have to buy to be used for LVDS? 2- How I can make the communication between the arty and the ADC chip? Is it only a wire or there is something else? 3- If I want more LVDS channels, can I use the I/O expansion module? Thank you.

Thank you very much for your reply.

Hello everyone, I'm trying to implement IOSERDES block as shown in the attachment on Vivado and couldn't find any idea on how to implement it by using IP blocks. The idea of my design is to enter 12 bits (000000111111) parallel input to (OSERDES) in DDR mode and then, 2 outputs (serialized data and clock) will be connected to (ISERDES) in DDR mode in order to generate again the same parallel input. A (check module) will be added to check if the received value after applying some delay is the same (000000111111) or not, and according to that, it will generate a signal to the BitSlip in the ISERDES to correct the output. I have read several documents but it was not obvious how to start implementing that. Also, I'm struggling with finding some tutorials to explain this step by step. So, could you please help me in detail if possible on how to implement this design? and how to convert the final blocks to Verilog code? I appreciate any help and sorry for the long post. Thank you in advance.