• Content Count

  • Joined

  • Last visited

  1. @[email protected] Yes,I've seen the article before,but I don't get the part that how to make it work for two counters,one that counts specifics numbers and one counts naturally after first counter and only using 2 digits S-S-D. @xc6lx45 This isn't quite a homework.I recently participated in a sort of hardware design tutoring class,and well,they'll come up a project once a while,and this is the one I couldn't solve. Well,still thanks for the extra fill-in on my subject. I don't expect others to finish it for me and just let me take it and go,what I do need is some clues and examples to help
  2. @Piasa , @[email protected] : What if I change the design to two counters,ditch the Moore machine? I mean,this generates the same end result,right? How to rewrite the initial code into this new design? I need a head start.
  3. @[email protected]: Thank you for your explicit explaining. I've read your recommended posts,that some information that need time to process. I noted that the code example in those posts are Verilog not sure what it has to do with VHDL...can Verilog's coding method be use on VHDL? I've considered using enable signal as well,I've set one under architecture named oscon (one_second_count_enable) just not sure how to apply it though. If I use this,can I apply CASE inside ? which logic in my design fit into this format? Moore ? 4 bit Counter? MUX ? decoder? And do I need to write a CASE sole
  4. First of all,Thank you for reply. And apology for the confusing sketch. Let me try to describe the initial design this way; First a CLK(50 MHZ) into a Frequency divider divide it down to (1 HZ) And then output (1 HZ) to drive the Designated Number "870107" Moore Machine For the 4 bit counter,When Moore Machine finished counting "870107" the 4 bit counter count 1, like Moore : 8>7>0>1>0>7
  5. Greetings. I just started out VHDL not long ago,and not quite familiar with Moore FSM. So I was trying to write this Moore FSM code as shown in Picture of my initial sketch(Link to imgur,safe to click). after search for some reference about Moore in VHDL,I'm still stuck. I'm hoping someone can help me fill-in the missing pieces of my code and to fit into the sketch. Sincerely Appreciate. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity M6B is Port ( clk : in STD_LOGIC; x : in STD_LOGIC;