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  1. Ram

    Xilinx SDK Templates echo server

    Hi jpeyron, thanks for your reply, actually in lwip echo server code, the tcp send buffer size is 8192 bytes, and it is fixed, but i need more size, becoze large number of data is transferring from zybo board to PC through ethernet, but due to limited size of send buffer only few data are receiving, i tried to change size 65536 bytes in system.mss file of board support package and it changed successfully, and rebuilding the program is successfully worked, and program is also successfully run on hardware but when i tried to make tcp connection via hercules utility tool. it said TCP connection timeout. i dont know why tcp connection is not made successfully by hercules, can you please help me out from this issue... thanks
  2. Hello everyone, can anyone please tell me the size of send buffer in echo server XSDK code and also in which header file it is mentioned ... your comments will be really helpful for me...please reply ... thanks Ram
  3. hello everyone, I am trying to run the HelloWorld application over Xilinx open-source Linux. in run configuration, I made a successful connection between pc and board via ssh only, but when I press run, it is producing an error... please find the attachment... can anyone please help me out from this issue... Thanks regards Ram
  4. hello everyone, after running open-source Linux through sd card over zynq zybo, I am trying to run hello world program using SDK via ethernet ... but I am failed to run HelloWorld can anyone tell me, how to change a setting into XSDK for running Linux application over Linux target. Thanks Regards Ram
  5. Hello Everyone i am trying to write 'C' code in sdk for matrix multplication ip of the order of 2*2. first of all i found verilog code of matrix multiplication , //Module for calculating Res = A*B //Where A,B and C are 2 by 2 matrices. module Mat_mult(A,B,Res); //input and output ports. //The size 32 bits which is 2*2=4 elements,each of which is 8 bits wide. input [31:0] A; input [31:0] B; output [31:0] Res; //internal variables reg [31:0] Res; reg [7:0] A1 [0:1][0:1]; reg [7:0] B1 [0:1][0:1]; reg [7:0] Res1 [0:1][0:1]; integer i,j,k; always@ (A or B) begin //Initialize the matrices-convert 1 D to 3D arrays {A1[0][0],A1[0][1],A1[1][0],A1[1][1]} = A; {B1[0][0],B1[0][1],B1[1][0],B1[1][1]} = B; i = 0; j = 0; k = 0; {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]} = 32'd0; //initialize to zeros. //Matrix multiplication for(i=0;i < 2;i=i+1) for(j=0;j < 2;j=j+1) for(k=0;k < 2;k=k+1) Res1[j] = Res1[j] + (A1[k] * B1[k][j]); //final output assignment - 3D array to 1D array conversion. Res = {Res1[0][0],Res1[0][1],Res1[1][0],Res1[1][1]}; end then i create ip in vivado .during ip creation part in user logic section i take two input A and B of 32 bit. then after that i create block design and generate bit stream . then i write following code in sdk .. #include "xparameters.h" #include "xil_io.h" #include "xbasic_types.h" #include <stdio.h> #include "myip_matix_Ani.h" #define MAT_A_ROWS 2 #define MAT_A_COLS 2 #define MAT_B_ROWS 2 #define MAT_B_COLS 2 int main() { int A[2][2], B[2][2],j, i; int C[2][2]; xil_printf("enter 4 numbers for A matrix\n"); for(i=0;i<2;i++) for(j=0;j<2;j++) scanf("%d", &A[j]); { Xil_Out32(XPAR_MYIP_MATIX_ANI_0_S00_AXI_BASEADDR+(j*sizeof(int)+i*MAT_A_ROWS*sizeof(int)), A[j]); } xil_printf("enter 4 numbers for B matrix\n"); for(i=0;i<2;i++) for(j=0;j<2;j++) scanf("%d", &B[j]); { Xil_Out32(XPAR_MYIP_MATIX_ANI_0_S00_AXI_BASEADDR+4+(j*sizeof(int)+i*MAT_A_ROWS*sizeof(int)), B[j]); } for(i=0;i<2;i++) for(j=0;j<2;j++) { C[j]= Xil_In32(XPAR_MYIP_MATIX_ANI_0_S00_AXI_BASEADDR+8+(j*sizeof(int)+i*MAT_A_ROWS*sizeof(int))); } xil_printf("{\r\n"); for (i = 0; i < MAT_A_ROWS; i++) for (j = 0; j < MAT_B_COLS; j++) xil_printf("%d\n",C[j]); } but this code is not generating correct results...everytime it generate wrong results ... can anyone please tell me what is the problem ... your reply would be really helpful for me . Thanks Ram
  6. hello guyz ... can anyone please tell me about ,,how to make partition into sd card ,,,for booting linux on zybo .......... Thanks Ram
  7. Ram

    what is need for zynq

    hello everyone why we need an processor and fpga on single chip , what are the separate advantages of processor and fpga thank-you regards Ram
  8. Ram


    hello everyone , i am little bit confused with one issue,, and the issue is when we launch c program from sdk to zynq ps ,(zybo), where it actually run , on dram which is externally connected through dram memory controller or it run directly on,, on-chip-memory.. any help for this thanks Ram
  9. Ram

    programming guide of zynq

    can anyone please tell me how to utilize programming guide instruction from zynq technical reference manual , like for every peripheral (uart, ethernet , spi, can,....etc...) programming guide is available in reference manual , just like i want to use ethernet controller by using mio pins , then how to initialize it .how to program ethernet for transferring data from pc to board ,,, thanks Best Regards Ram
  10. Ram

    spi zynq

    Hi,jon can you explain this code in more detail ,, it is like command line argument Thank-you Ram
  11. Ram

    vivado 2017.4

    Thank-you melisha ,,it is working Ram
  12. Ram

    vivado 2017.4

    hi, jon actually for a very first time when i create block design and use this c code (which i mentioned earlier ) , sdk was working , it was printing on sdk terminal ,, but after few hours , i use again this code , then it was not working ,, second time i am facing this problem , when i was using uart communication , i faced similar problem.......... thanks anyway ..... ram
  13. Ram

    vivado 2017.4

    hey , anybody found any solution for SDK terminal thanks Ram
  14. Ram

    vivado 2017.4

    Hey @jon Pls , reply What can we do for this issue Thanks RAM
  15. Ram

    ethernet communication

    ya ,, i am looking for this kind of terminal for linux